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Debug probe for three c6671s

Hello,

I have some questions about debug probe for three c6671s.

Q1> If three DSPs are independently connected to debug probe like 'device-independent trace configuration', can CCS access three DSPs at once?

Q2> Can I use either XDS100 or XDS200 for debugging c6671? If I can, what is the restriction comparing to XDS560v2?

Q3> Can I configure single or parallel trace by XDS200?

Q4> c6671 has 19 emulation ports(EMU00~EMU18). When I configure trace with XDS560v2, should I connect all emulation port pins? What is minimum pin number for signle/parallel trace?

Q5> When I configure parallel trace with XDS560v2, what is the advantage comparing to single trace?

Q6> When I connect three DSPs over SRIO or PCIe for sharing each DSP's memory, which trace configuration can access all memories of  three DSPs?

  • Hi,

    Moved your thread to CCS forum for faster response.

    Thank you.

  • Hi,

    1) I am not 100% sure what you mean by "device-independent trace configuration"... You mean you are connecting to three devices using a trace pod each? If so, it is possible to configure a target configuration with three emulators and connect to each on a single CCS session, but in my opinion I would open three instances of CCS instead (with different workspaces), as you will possibly run into memory limitations (each instance can use up to 2GB limited by the 32-bit JVM).

    2) Yes. There are no restrictions for debugging per se. The XDS560v2 is a more featured emulator that allows performing System Trace. For details, check these two videos:

    3) Sorry, I am unsure what you mean by serial or parallel trace. If by parallel you mean exporting trace information through external pins (also called pin trace) then XDS200 does not support it. Check the videos above for details on what is supported and advantages.

    4) Check the second video, which talks about the hardware connections that each emulation technology uses. Since the XDS560v2 is capable of System Trace via external pins, it only uses up to EMU4.

    5) Considering my answer to 3) above, check the videos for the details and advantages. Typically pin trace allows for larger buffers when compared to ETB

    6) Unfortunately I am not familiar with the memory sharing mechanism of SRIO. 

    A few additional details can be seen in the links below:

    http://www.ti.com/lit/ug/sprugz2a/sprugz2a.pdf

    http://processors.wiki.ti.com/index.php/CCS_Modules_Library#Real-time_Trace_for_Keystone_Devices

    Hope this helps,

    Rafael