I'm using CCSv4 for multi-core C6474 simulation. But it frequently hangs when I load the program or even when I edit the variable names in the watch window, and after terminating the CCS, an exit window with "JVM terminated. Exit code=1073807364" is present! I googled the error message and revised the eclipse.ini in the eclipse installation directory to enlarge the JVM heap size. But it doesn't work!
I used CCSv3.3 before to simulate the programs running in the three cores of C6474, and the CCS always hangs when a core runs after another! So I turned to the new CCSv4, and now I think there's little improvement in the simulation. At first, I try to access the other core's on-chip memory after the other core's initialization, so I thought the violation access of the other core's on-chip memory may be the reason to cause the termination of the simulation, and I change the access to off-chip, but it doesn't work! The CCS IDE hangs just as before!
So would anyone who used the CCS to simulate C6474 tell me how to simulate the multi-core, or only emulation is available? The gel I used is the default gel file named 'tisim_init_6474.gel' and the cfg file is 'tisim_c6474_symmetric.cfg'! When using CCSv3.3, I replaced the cfg files with the errata files listed on http://wiki.davincidsp.com/index.php?title=CCSv3.3_SR12_Simulation_Errata! I've no idea to solve the frequently no-response of the CCS simulator, and I don't know if the emulator has the same problem!
Digital Signal Processing, ARM DSPs, Embedded System, Multi-core Programming
Could you provide a detailed test case? I've used both the C6474 and other similar multi-core simulators without seeing the issues you are reporting. Step-by-step instructions to consistently reproduce the issue would help us greatly in trying to resolve the issue.
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We are aware of this problem in multi-core Cycle accurate simulator. The problem is due to a dead-lock in SCR, this happens when one core is running & other cores are at halted state, the core that is running will clock the SCR and if another core has already placed a request on SCR & not ready to accept the request because it's on halted state, this results in dead-lock & hangs the simulator. We are working on the fix & the fix is expected to be available in CCSv4 RTM.
As a work around, if you do sync run on all core you can avoid dead-lock & the hang.
If my reply answers your question please mark the thread as answered
Check the Wiki for more info - link
For example, coreA read the on-chip data of CoreA and process it, the result is written to coreB, coneB reads the written result and port the results to coreC, coreC read the results processed by CoreB and write the result to CoreA! No matter I placed the exchanged data between cores in on-chip or off-chip memory, the CCS frequently hangs while I debug the simulation! I find it really hard to see whether the data is correct because before the data is generated, the CCS requires to be terminated. I don't know whether the emulator can do the debug work core by core!
Thanks for your reply! I've tried sync-run, but the CCS hangs, too! and with Sync run, how can I debug the simulation? When setting the breakpoints in the program, it seldom reaches the breakpoint before the termination of the CCS IDE!
I am surprised it still hangs. Which version of CCS you are using? About debugging sync run, enable the global breakpoint in the PDM, which will halt all the core when breakpoint is hit on any of the cores. Then you can check the status of memory & registers on individual CCS IDE. Apply breakpoint in all the cores & check the data before written to the memory, is the best way to debug.
About the emulator, i need to check with my colleagues & get back to you.
I've used CCSv3.3 with SR12 patched and CCSv4 Beta 5, the same problem exists! The problem for sync-run is probably because the configuration of the on-chip memory isn't known by the other cores, and there exists violated access of unstalbe on-chip memory! But what trouble me most is the CCS may hang when I load program to one core or when all core halt and I revise the watch variables to get their address! Thanks for your reply and look forward to your further conclusion of the emulator case!
When sync-run, it needs to halt once or twice before the multi-core run! The program diagram is as follows: coreA processes data and writes a finish flag to coreB, and CoreB reads the flag util '1' and begins to process data and writes a finish flag to CoreC, CoreC reads the flags and processes and write a finish flag to CoreA! The flag for CoreA is initialized to 1, so the three cores should run synchronously! But it often occurs that coreA refuses to run, and I halt the simulator and sync-run again, this time maybe all cores run sequentially! Is this the bug of the simulator then?
I don't think it's a bug on simulator. I think the IDE is taking some time to update the status. When you do sync-run it equivalent to multiple thread running simultanously, so flag status on each core will be different & you might want to check for race & dead lock conditions in programming.
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