Hello,
I am using c6416 functional simulator and all sections of code are mapped to internal memory(L2SRAM) in linker command file. My questions are:
-Is cache operation disabled by default for internal memory? If not, then how to turn it off for internal memory?
-spru610c says that external memory is by default not cacheable and we can configure it as cacheable by setting the CE bit in corresponding MAR register. But if I modify linker file and map all code sections to EMFIACE0 space(external memory) and then profile the code for cache events, even then it shows events like hit, miss for L1 cache... shouldn't it be non cacheable? or simulator shows some different behaviuor?