Hi,
I am using c6416 functional simulator in CCSv5.5. I am profiling the code using functional profiler for three cases. In first, all data sections were mapped to L2SRAM(cacheable by default) and L2 cache was disabled, in second all code sections mapped to EMIFACE0(external memory) which was non-cacheable by default and L2 cache still disabled, in third all code sections mapped to EMFIACE0 which was configured as cacheable using CSL and L2 was also configured as cache of 256KB using CSL.
For all three cases, functional profiler shows same cpu cycle count, whereas I believe CPU cycle count should increase if cache is disabled and all data is to be feteched from external memory space.