IAR Workbench Code to CCSv6 Conversion

rohit warule said:

_P1DIR ./source/Emeter_Init.obj
_P1OUT ./source/Emeter_Main.obj
_P2DIR ./source/Emeter_Init.obj
_P2OUT ./source/Emeter_Init.obj

P1DIR, P1OUT, P2DIR and P2OUT are MSP430 peripheral registers, which should be referenced in the linker command file in the project. Does the lnk_msp430afe252.cmd file in the project contain the following?

/****************************************************************************/
/* Include peripherals memory map                                           */
/****************************************************************************/

-l msp430afe252.cmd

Thanks Chester Gillon,
i solved that issue ,but i am facing some another issue can any one help for this ,i have converted my IAR code to CCSv6 ,but getting this below issue.
i think this is compiler syntax issue
the below line is written in IAR ide


#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
#error msp430f6736.h file use with ICC430/A430 only
#endif

so how can i write it in CCSv6 ,to solve this ,
is there any other issue ,please help me to solve this .........



**** Build of configuration Debug for project AV_Prepaid_F6736 ****

"C:\\ti\\ccsv6\\utils\\bin\\gmake" -k all
'Building file: ../Blink.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Blink.pp" "../Blink.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Blink.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Blink.obj] Error 1
'Building file: ../Emeter_Calib.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Calib.pp" "../Emeter_Calib.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Calib.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Calib.obj] Error 1
'Building file: ../Emeter_Display.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Display.pp" "../Emeter_Display.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Display.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Display.obj] Error 1
'Building file: ../Emeter_Eeprom_RW.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Eeprom_RW.pp" "../Emeter_Eeprom_RW.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Eeprom_RW.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Eeprom_RW.obj] Error 1
'Building file: ../Emeter_FIR_Param.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_FIR_Param.pp" "../Emeter_FIR_Param.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_FIR_Param.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_FIR_Param.obj] Error 1
'Building file: ../Emeter_Functions.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Functions.pp" "../Emeter_Functions.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Functions.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Functions.obj] Error 1
'Building file: ../Emeter_Init.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Init.pp" "../Emeter_Init.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Init.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Init.obj] Error 1
'Building file: ../Emeter_Interrupts.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Interrupts.pp" "../Emeter_Interrupts.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Interrupts.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Interrupts.obj] Error 1
'Building file: ../Emeter_Key_Init.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Key_Init.pp" "../Emeter_Key_Init.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Key_Init.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Key_Init.obj] Error 1
'Building file: ../Emeter_MD_Store.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_MD_Store.pp" "../Emeter_MD_Store.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_MD_Store.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_MD_Store.obj] Error 1
'Building file: ../Emeter_Main.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_Main.pp" "../Emeter_Main.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_Main.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_Main.obj] Error 1
'Building file: ../Emeter_RTC.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Emeter_RTC.pp" "../Emeter_RTC.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Emeter_RTC.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Emeter_RTC.obj] Error 1
'Building file: ../IR_Communication.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="IR_Communication.pp" "../IR_Communication.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../IR_Communication.c".
Compilation terminated.

>> Compilation failure
gmake: *** [IR_Communication.obj] Error 1
'Building file: ../MD_Calculation.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="MD_Calculation.pp" "../MD_Calculation.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../MD_Calculation.c".
Compilation terminated.

>> Compilation failure
gmake: *** [MD_Calculation.obj] Error 1
'Building file: ../Mag_Tamp_duration.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Mag_Tamp_duration.pp" "../Mag_Tamp_duration.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Mag_Tamp_duration.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Mag_Tamp_duration.obj] Error 1
'Building file: ../Month_Overflow_Check.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Month_Overflow_Check.pp" "../Month_Overflow_Check.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Month_Overflow_Check.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Month_Overflow_Check.obj] Error 1
'Building file: ../RESET_EEPROM_READ.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="RESET_EEPROM_READ.pp" "../RESET_EEPROM_READ.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../RESET_EEPROM_READ.c".
Compilation terminated.
gmake: *** [RESET_EEPROM_READ.obj] Error 1

>> Compilation failure
'Building file: ../RTC_RD_WR.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="RTC_RD_WR.pp" "../RTC_RD_WR.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../RTC_RD_WR.c".
Compilation terminated.

>> Compilation failure
gmake: *** [RTC_RD_WR.obj] Error 1
'Building file: ../Tamper_Storage.c'
'Invoking: MSP430 Compiler'
"C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/bin/cl430" -vmspx --abi=eabi --data_model=restricted --use_hw_mpy=F5 --include_path="C:/ti/ccsv6/ccs_base/msp430/include" --include_path="C:/ti/ccsv6/tools/compiler/ti-cgt-msp430_4.4.3/include" --advice:power=all -g --define=__MSP430F6736__ --diag_warning=225 --display_error_number --diag_wrap=off --silicon_errata=CPU21 --silicon_errata=CPU22 --silicon_errata=CPU40 --printf_support=minimal --preproc_with_compile --preproc_dependency="Tamper_Storage.pp" "../Tamper_Storage.c"
"..\msp430F6736_modified.h", line 29: fatal error #35: #error directive: msp430f6736.h file use with ICC430/A430 only
1 catastrophic error detected in the compilation of "../Tamper_Storage.c".
Compilation terminated.

>> Compilation failure
gmake: *** [Tamper_Storage.obj] Error 1
gmake: Target `all' not remade because of errors.

**** Build Finished ****

rohit warule said:

#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
#error msp430f6736.h file use with ICC430/A430 only
 #endif

That means the source file was only intended to be compiled with the IAR MSP430 compiler.

rohit warule said:

so how can i write it in CCSv6 ,to solve this ,

More context is required to determine how to convert the project to CCS. Is this a standard example project, and if so where can the project be downloaded from?

Thanks Chester Gillon,

Actually i am working on Prepaid Meter System and we have taken Ti solution for this project , we are using the controller MSP430F6736 ,i have already converted other files to CCSv6 supported files from IAR code , i know hoe to convert IAR to CCS , done for multiples codes ,but facing some issue for below file .
please see the below #include "msp430F6736_modified.h"......

please let me know i am doing some wrong things .....














/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for the
* MSP430F6736 device.
*
* Texas Instruments, Version 1.2
*
* Rev. 1.0, Initial Release
* Rev. 1.1, Added missing LCD Registers
* Rev. 1.2, Fixed typo in LCD_C (VLCD) definitions
*
********************************************************************/

#ifndef __MSP430F6736
#define __MSP430F6736

#define __MSP430_HEADER_VERSION__ 1065 /* Beta-Build-Tag: #0023 */

#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif

#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
#error msp430f6736.h file for use with ICC430/A430 only
#endif


#ifdef __IAR_SYSTEMS_ICC__
#include "in430.h"
#pragma language=extended

#define DEFC(name, address) __no_init volatile unsigned char name @ address;
#define DEFW(name, address) __no_init volatile unsigned short name @ address;

#define DEFCW(name, address) __no_init union \
{ \
struct \
{ \
volatile unsigned char name##_L; \
volatile unsigned char name##_H; \
}; \
volatile unsigned short name; \
} @ address;

#define READ_ONLY_DEFCW(name, address) __no_init union \
{ \
struct \
{ \
volatile READ_ONLY unsigned char name##_L; \
volatile READ_ONLY unsigned char name##_H; \
}; \
volatile READ_ONLY unsigned short name; \
} @ address;


#if __REGISTER_MODEL__ == __REGISTER_MODEL_REG20__
#define __ACCESS_20BIT_REG__ void __data20 * volatile
#else
#define __ACCESS_20BIT_REG__ volatile unsigned short /* only short access from C is allowed in small memory model */
#endif

#define DEFA(name, address) __no_init union \
{ \
struct \
{ \
volatile unsigned char name##_L; \
volatile unsigned char name##_H; \
}; \
struct \
{ \
volatile unsigned short name##L; \
volatile unsigned short name##H; \
}; \
__ACCESS_20BIT_REG__ name; \
} @ address;

#endif /* __IAR_SYSTEMS_ICC__ */


#ifdef __IAR_SYSTEMS_ASM__
#define DEFC(name, address) sfrb name = address;
#define DEFW(name, address) sfrw name = address;

#define DEFCW(name, address) sfrbw name, name##_L, name##_H, address;
sfrbw macro name, name_L, name_H, address;
sfrb name_L = address;
sfrb name_H = address+1;
sfrw name = address;
endm

#define READ_ONLY_DEFCW(name, address) const_sfrbw name, name##_L, name##_H, address;
const_sfrbw macro name, name_L, name_H, address;
const sfrb name_L = address;
const sfrb name_H = address+1;
const sfrw name = address;
endm

#define DEFA(name, address) sfrba name, name##L, name##H, name##_L, name##_H, address;
sfrba macro name, nameL, nameH, name_L, name_H, address;
sfrb name_L = address;
sfrb name_H = address+1;
sfrw nameL = address;
sfrw nameH = address+2;
sfrl name = address;
endm

#endif /* __IAR_SYSTEMS_ASM__*/

#ifdef __cplusplus
#define READ_ONLY
#else
#define READ_ONLY const
#endif

/************************************************************
* STANDARD BITS
************************************************************/

#define BIT0 (0x0001u)
#define BIT1 (0x0002u)
#define BIT2 (0x0004u)
#define BIT3 (0x0008u)
#define BIT4 (0x0010u)
#define BIT5 (0x0020u)
#define BIT6 (0x0040u)
#define BIT7 (0x0080u)
#define BIT8 (0x0100u)
#define BIT9 (0x0200u)
#define BITA (0x0400u)
#define BITB (0x0800u)
#define BITC (0x1000u)
#define BITD (0x2000u)
#define BITE (0x4000u)
#define BITF (0x8000u)

/************************************************************
* STATUS REGISTER BITS
************************************************************/

#define C (0x0001u)
#define Z (0x0002u)
#define N (0x0004u)
#define V (0x0100u)
#define GIE (0x0008u)
#define CPUOFF (0x0010u)
#define OSCOFF (0x0020u)
#define SCG0 (0x0040u)
#define SCG1 (0x0080u)

/* Low Power Modes coded with Bits 4-7 in SR */

#ifndef __IAR_SYSTEMS_ICC__ /* Begin #defines for assembler */
#define LPM0 (CPUOFF)
#define LPM1 (SCG0+CPUOFF)
#define LPM2 (SCG1+CPUOFF)
#define LPM3 (SCG1+SCG0+CPUOFF)
#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
/* End #defines for assembler */

#else /* Begin #defines for C */
#define LPM0_bits (CPUOFF)
#define LPM1_bits (SCG0+CPUOFF)
#define LPM2_bits (SCG1+CPUOFF)
#define LPM3_bits (SCG1+SCG0+CPUOFF)
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)

#include "in430.h"

#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
#endif /* End #defines for C */

/************************************************************
* CPU
************************************************************/
#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */

/************************************************************
* PERIPHERAL FILE MAP
************************************************************/

/************************************************************
* ADC10_A
************************************************************/
#define __MSP430_HAS_ADC10_A__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_ADC10_A__ 0x0740

#define ADC10CTL0_ (0x0740u) /* ADC10 Control 0 */
DEFCW( ADC10CTL0 , ADC10CTL0_)
#define ADC10CTL1_ (0x0742u) /* ADC10 Control 1 */
DEFCW( ADC10CTL1 , ADC10CTL1_)
#define ADC10CTL2_ (0x0744u) /* ADC10 Control 2 */
DEFCW( ADC10CTL2 , ADC10CTL2_)
#define ADC10LO_ (0x0746u) /* ADC10 Window Comparator High Threshold */
DEFCW( ADC10LO , ADC10LO_)
#define ADC10HI_ (0x0748u) /* ADC10 Window Comparator High Threshold */
DEFCW( ADC10HI , ADC10HI_)
#define ADC10MCTL0_ (0x074Au) /* ADC10 Memory Control 0 */
DEFCW( ADC10MCTL0 , ADC10MCTL0_)
#define ADC10MEM0_ (0x0752u) /* ADC10 Conversion Memory 0 */
DEFCW( ADC10MEM0 , ADC10MEM0_)
#define ADC10IE_ (0x075Au) /* ADC10 Interrupt Enable */
DEFCW( ADC10IE , ADC10IE_)
#define ADC10IFG_ (0x075Cu) /* ADC10 Interrupt Flag */
DEFCW( ADC10IFG , ADC10IFG_)
#define ADC10IV_ (0x075Eu) /* ADC10 Interrupt Vector Word */
DEFCW( ADC10IV , ADC10IV_)

/* ADC10CTL0 Control Bits */
#define ADC10SC (0x0001u) /* ADC10 Start Conversion */
#define ADC10ENC (0x0002u) /* ADC10 Enable Conversion */
#define ADC10ON (0x0010u) /* ADC10 On/enable */
#define ADC10MSC (0x0080u) /* ADC10 Multiple SampleConversion */
#define ADC10SHT0 (0x0100u) /* ADC10 Sample Hold Select Bit: 0 */
#define ADC10SHT1 (0x0200u) /* ADC10 Sample Hold Select Bit: 1 */
#define ADC10SHT2 (0x0400u) /* ADC10 Sample Hold Select Bit: 2 */
#define ADC10SHT3 (0x0800u) /* ADC10 Sample Hold Select Bit: 3 */

/* ADC10CTL0 Control Bits */
#define ADC10SC_L (0x0001u) /* ADC10 Start Conversion */
#define ADC10ENC_L (0x0002u) /* ADC10 Enable Conversion */
#define ADC10ON_L (0x0010u) /* ADC10 On/enable */
#define ADC10MSC_L (0x0080u) /* ADC10 Multiple SampleConversion */

/* ADC10CTL0 Control Bits */
#define ADC10SHT0_H (0x0001u) /* ADC10 Sample Hold Select Bit: 0 */
#define ADC10SHT1_H (0x0002u) /* ADC10 Sample Hold Select Bit: 1 */
#define ADC10SHT2_H (0x0004u) /* ADC10 Sample Hold Select Bit: 2 */
#define ADC10SHT3_H (0x0008u) /* ADC10 Sample Hold Select Bit: 3 */

#define ADC10SHT_0 (0*0x100u) /* ADC10 Sample Hold Select 0 */
#define ADC10SHT_1 (1*0x100u) /* ADC10 Sample Hold Select 1 */
#define ADC10SHT_2 (2*0x100u) /* ADC10 Sample Hold Select 2 */
#define ADC10SHT_3 (3*0x100u) /* ADC10 Sample Hold Select 3 */
#define ADC10SHT_4 (4*0x100u) /* ADC10 Sample Hold Select 4 */
#define ADC10SHT_5 (5*0x100u) /* ADC10 Sample Hold Select 5 */
#define ADC10SHT_6 (6*0x100u) /* ADC10 Sample Hold Select 6 */
#define ADC10SHT_7 (7*0x100u) /* ADC10 Sample Hold Select 7 */
#define ADC10SHT_8 (8*0x100u) /* ADC10 Sample Hold Select 8 */
#define ADC10SHT_9 (9*0x100u) /* ADC10 Sample Hold Select 9 */
#define ADC10SHT_10 (10*0x100u) /* ADC10 Sample Hold Select 10 */
#define ADC10SHT_11 (11*0x100u) /* ADC10 Sample Hold Select 11 */
#define ADC10SHT_12 (12*0x100u) /* ADC10 Sample Hold Select 12 */
#define ADC10SHT_13 (13*0x100u) /* ADC10 Sample Hold Select 13 */
#define ADC10SHT_14 (14*0x100u) /* ADC10 Sample Hold Select 14 */
#define ADC10SHT_15 (15*0x100u) /* ADC10 Sample Hold Select 15 */

/* ADC10CTL1 Control Bits */
#define ADC10BUSY (0x0001u) /* ADC10 Busy */
#define ADC10CONSEQ0 (0x0002u) /* ADC10 Conversion Sequence Select 0 */
#define ADC10CONSEQ1 (0x0004u) /* ADC10 Conversion Sequence Select 1 */
#define ADC10SSEL0 (0x0008u) /* ADC10 Clock Source Select 0 */
#define ADC10SSEL1 (0x0010u) /* ADC10 Clock Source Select 1 */
#define ADC10DIV0 (0x0020u) /* ADC10 Clock Divider Select 0 */
#define ADC10DIV1 (0x0040u) /* ADC10 Clock Divider Select 1 */
#define ADC10DIV2 (0x0080u) /* ADC10 Clock Divider Select 2 */
#define ADC10ISSH (0x0100u) /* ADC10 Invert Sample Hold Signal */
#define ADC10SHP (0x0200u) /* ADC10 Sample/Hold Pulse Mode */
#define ADC10SHS0 (0x0400u) /* ADC10 Sample/Hold Source 0 */
#define ADC10SHS1 (0x0800u) /* ADC10 Sample/Hold Source 1 */

/* ADC10CTL1 Control Bits */
#define ADC10BUSY_L (0x0001u) /* ADC10 Busy */
#define ADC10CONSEQ0_L (0x0002u) /* ADC10 Conversion Sequence Select 0 */
#define ADC10CONSEQ1_L (0x0004u) /* ADC10 Conversion Sequence Select 1 */
#define ADC10SSEL0_L (0x0008u) /* ADC10 Clock Source Select 0 */
#define ADC10SSEL1_L (0x0010u) /* ADC10 Clock Source Select 1 */
#define ADC10DIV0_L (0x0020u) /* ADC10 Clock Divider Select 0 */
#define ADC10DIV1_L (0x0040u) /* ADC10 Clock Divider Select 1 */
#define ADC10DIV2_L (0x0080u) /* ADC10 Clock Divider Select 2 */

/* ADC10CTL1 Control Bits */
#define ADC10ISSH_H (0x0001u) /* ADC10 Invert Sample Hold Signal */
#define ADC10SHP_H (0x0002u) /* ADC10 Sample/Hold Pulse Mode */
#define ADC10SHS0_H (0x0004u) /* ADC10 Sample/Hold Source 0 */
#define ADC10SHS1_H (0x0008u) /* ADC10 Sample/Hold Source 1 */

#define ADC10CONSEQ_0 (0*2u) /* ADC10 Conversion Sequence Select: 0 */
#define ADC10CONSEQ_1 (1*2u) /* ADC10 Conversion Sequence Select: 1 */
#define ADC10CONSEQ_2 (2*2u) /* ADC10 Conversion Sequence Select: 2 */
#define ADC10CONSEQ_3 (3*2u) /* ADC10 Conversion Sequence Select: 3 */

#define ADC10SSEL_0 (0*8u) /* ADC10 Clock Source Select: 0 */
#define ADC10SSEL_1 (1*8u) /* ADC10 Clock Source Select: 1 */
#define ADC10SSEL_2 (2*8u) /* ADC10 Clock Source Select: 2 */
#define ADC10SSEL_3 (3*8u) /* ADC10 Clock Source Select: 3 */

#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select: 0 */
#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select: 1 */
#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select: 2 */
#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select: 3 */
#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select: 4 */
#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select: 5 */
#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select: 6 */
#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select: 7 */

#define ADC10SHS_0 (0*0x400u) /* ADC10 Sample/Hold Source: 0 */
#define ADC10SHS_1 (1*0x400u) /* ADC10 Sample/Hold Source: 1 */
#define ADC10SHS_2 (2*0x400u) /* ADC10 Sample/Hold Source: 2 */
#define ADC10SHS_3 (3*0x400u) /* ADC10 Sample/Hold Source: 3 */

/* ADC10CTL2 Control Bits */
#define ADC10REFBURST (0x0001u) /* ADC10 Reference Burst */
#define ADC10SR (0x0004u) /* ADC10 Sampling Rate */
#define ADC10DF (0x0008u) /* ADC10 Data Format */
#define ADC10RES (0x0010u) /* ADC10 Resolution Bit */
#define ADC10PDIV0 (0x0100u) /* ADC10 predivider Bit: 0 */
#define ADC10PDIV1 (0x0200u) /* ADC10 predivider Bit: 1 */

/* ADC10CTL2 Control Bits */
#define ADC10REFBURST_L (0x0001u) /* ADC10 Reference Burst */
#define ADC10SR_L (0x0004u) /* ADC10 Sampling Rate */
#define ADC10DF_L (0x0008u) /* ADC10 Data Format */
#define ADC10RES_L (0x0010u) /* ADC10 Resolution Bit */

/* ADC10CTL2 Control Bits */
#define ADC10PDIV0_H (0x0001u) /* ADC10 predivider Bit: 0 */
#define ADC10PDIV1_H (0x0002u) /* ADC10 predivider Bit: 1 */

#define ADC10PDIV_0 (0x0000u) /* ADC10 predivider /1 */
#define ADC10PDIV_1 (0x0100u) /* ADC10 predivider /2 */
#define ADC10PDIV_2 (0x0200u) /* ADC10 predivider /64 */
#define ADC10PDIV_3 (0x0300u) /* ADC10 predivider reserved */

#define ADC10PDIV__1 (0x0000u) /* ADC10 predivider /1 */
#define ADC10PDIV__4 (0x0100u) /* ADC10 predivider /2 */
#define ADC10PDIV__64 (0x0200u) /* ADC10 predivider /64 */

/* ADC10MCTL0 Control Bits */
#define ADC10INCH0 (0x0001u) /* ADC10 Input Channel Select Bit 0 */
#define ADC10INCH1 (0x0002u) /* ADC10 Input Channel Select Bit 1 */
#define ADC10INCH2 (0x0004u) /* ADC10 Input Channel Select Bit 2 */
#define ADC10INCH3 (0x0008u) /* ADC10 Input Channel Select Bit 3 */
#define ADC10SREF0 (0x0010u) /* ADC10 Select Reference Bit 0 */
#define ADC10SREF1 (0x0020u) /* ADC10 Select Reference Bit 1 */
#define ADC10SREF2 (0x0040u) /* ADC10 Select Reference Bit 2 */

/* ADC10MCTL0 Control Bits */
#define ADC10INCH0_L (0x0001u) /* ADC10 Input Channel Select Bit 0 */
#define ADC10INCH1_L (0x0002u) /* ADC10 Input Channel Select Bit 1 */
#define ADC10INCH2_L (0x0004u) /* ADC10 Input Channel Select Bit 2 */
#define ADC10INCH3_L (0x0008u) /* ADC10 Input Channel Select Bit 3 */
#define ADC10SREF0_L (0x0010u) /* ADC10 Select Reference Bit 0 */
#define ADC10SREF1_L (0x0020u) /* ADC10 Select Reference Bit 1 */
#define ADC10SREF2_L (0x0040u) /* ADC10 Select Reference Bit 2 */

/* ADC10MCTL0 Control Bits */

#define ADC10INCH_0 (0) /* ADC10 Input Channel 0 */
#define ADC10INCH_1 (1) /* ADC10 Input Channel 1 */
#define ADC10INCH_2 (2) /* ADC10 Input Channel 2 */
#define ADC10INCH_3 (3) /* ADC10 Input Channel 3 */
#define ADC10INCH_4 (4) /* ADC10 Input Channel 4 */
#define ADC10INCH_5 (5) /* ADC10 Input Channel 5 */
#define ADC10INCH_6 (6) /* ADC10 Input Channel 6 */
#define ADC10INCH_7 (7) /* ADC10 Input Channel 7 */
#define ADC10INCH_8 (8) /* ADC10 Input Channel 8 */
#define ADC10INCH_9 (9) /* ADC10 Input Channel 9 */
#define ADC10INCH_10 (10) /* ADC10 Input Channel 10 */
#define ADC10INCH_11 (11) /* ADC10 Input Channel 11 */
#define ADC10INCH_12 (12) /* ADC10 Input Channel 12 */
#define ADC10INCH_13 (13) /* ADC10 Input Channel 13 */
#define ADC10INCH_14 (14) /* ADC10 Input Channel 14 */
#define ADC10INCH_15 (15) /* ADC10 Input Channel 15 */

#define ADC10SREF_0 (0*0x10u) /* ADC10 Select Reference 0 */
#define ADC10SREF_1 (1*0x10u) /* ADC10 Select Reference 1 */
#define ADC10SREF_2 (2*0x10u) /* ADC10 Select Reference 2 */
#define ADC10SREF_3 (3*0x10u) /* ADC10 Select Reference 3 */
#define ADC10SREF_4 (4*0x10u) /* ADC10 Select Reference 4 */
#define ADC10SREF_5 (5*0x10u) /* ADC10 Select Reference 5 */
#define ADC10SREF_6 (6*0x10u) /* ADC10 Select Reference 6 */
#define ADC10SREF_7 (7*0x10u) /* ADC10 Select Reference 7 */

/* ADC10IE Interrupt Enable Bits */
#define ADC10IE0 (0x0001u) /* ADC10_A Interrupt enable */
#define ADC10INIE (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
#define ADC10LOIE (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
#define ADC10HIIE (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
#define ADC10OVIE (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */
#define ADC10TOVIE (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */

/* ADC10IE Interrupt Enable Bits */
#define ADC10IE0_L (0x0001u) /* ADC10_A Interrupt enable */
#define ADC10INIE_L (0x0002u) /* ADC10_A Interrupt enable for the inside of window of the Window comparator */
#define ADC10LOIE_L (0x0004u) /* ADC10_A Interrupt enable for lower threshold of the Window comparator */
#define ADC10HIIE_L (0x0008u) /* ADC10_A Interrupt enable for upper threshold of the Window comparator */
#define ADC10OVIE_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt enable */
#define ADC10TOVIE_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt enable */

/* ADC10IE Interrupt Enable Bits */

/* ADC10IFG Interrupt Flag Bits */
#define ADC10IFG0 (0x0001u) /* ADC10_A Interrupt Flag */
#define ADC10INIFG (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
#define ADC10LOIFG (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
#define ADC10HIIFG (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
#define ADC10OVIFG (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */
#define ADC10TOVIFG (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */

/* ADC10IFG Interrupt Flag Bits */
#define ADC10IFG0_L (0x0001u) /* ADC10_A Interrupt Flag */
#define ADC10INIFG_L (0x0002u) /* ADC10_A Interrupt Flag for the inside of window of the Window comparator */
#define ADC10LOIFG_L (0x0004u) /* ADC10_A Interrupt Flag for lower threshold of the Window comparator */
#define ADC10HIIFG_L (0x0008u) /* ADC10_A Interrupt Flag for upper threshold of the Window comparator */
#define ADC10OVIFG_L (0x0010u) /* ADC10_A ADC10MEM overflow Interrupt Flag */
#define ADC10TOVIFG_L (0x0020u) /* ADC10_A conversion-time-overflow Interrupt Flag */

/* ADC10IFG Interrupt Flag Bits */

/* ADC10IV Definitions */
#define ADC10IV_NONE (0x0000u) /* No Interrupt pending */
#define ADC10IV_ADC10OVIFG (0x0002u) /* ADC10OVIFG */
#define ADC10IV_ADC10TOVIFG (0x0004u) /* ADC10TOVIFG */
#define ADC10IV_ADC10HIIFG (0x0006u) /* ADC10HIIFG */
#define ADC10IV_ADC10LOIFG (0x0008u) /* ADC10LOIFG */
#define ADC10IV_ADC10INIFG (0x000Au) /* ADC10INIFG */
#define ADC10IV_ADC10IFG (0x000Cu) /* ADC10IFG */

/************************************************************
* Auxilary Supply
************************************************************/
#define __MSP430_HAS_AUX_SUPPLY__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_AUX_SUPPLY__ 0x09E0

#define AUXCTL0_ (0x09E0u) /* Auxiliary Supply Control register 0 */
DEFCW( AUXCTL0 , AUXCTL0_)
#define AUXCTL1_ (0x09E2u) /* Auxiliary Supply Control register 1 */
DEFCW( AUXCTL1 , AUXCTL1_)
#define AUXCTL2_ (0x09E4u) /* Auxiliary Supply Control register 2 */
DEFCW( AUXCTL2 , AUXCTL2_)

#define AUX2CHCTL_ (0x09F2u) /* AUX2 Charger Control register */
DEFCW( AUX2CHCTL , AUX2CHCTL_)
#define AUX3CHCTL_ (0x09F4u) /* AUX3 Charger Control register */
DEFCW( AUX3CHCTL , AUX3CHCTL_)
#define AUXADCCTL_ (0x09F6u) /* AUX ADC Control */
DEFCW( AUXADCCTL , AUXADCCTL_)
#define AUXIFG_ (0x09FAu) /* AUX Interrupt Flag */
DEFCW( AUXIFG , AUXIFG_)
#define AUXIE_ (0x09FCu) /* AUX Interrupt Enable */
DEFCW( AUXIE , AUXIE_)
#define AUXIV_ (0x09FEu) /* AUX Interrupt Vector Word */
DEFCW( AUXIV , AUXIV_)

/* AUXCTL0 Control Bits */
#define LOCKAUX (0x0001u) /* Lock auxiliary supply system. */
#define AUX0SW (0x0002u) /* DVCC switch state. */
#define AUX1SW (0x0004u) /* AUX1 switch state. */
#define AUX2SW (0x0008u) /* AUX2 switch state. */

/* AUXCTL0 Control Bits */
#define LOCKAUX_L (0x0001u) /* Lock auxiliary supply system. */
#define AUX0SW_L (0x0002u) /* DVCC switch state. */
#define AUX1SW_L (0x0004u) /* AUX1 switch state. */
#define AUX2SW_L (0x0008u) /* AUX2 switch state. */

/* AUXCTL0 Control Bits */

#define AUXKEY (0xA500u) /* AUX Key */
#define AUXKEY_H (0xA5) /* AUX Key (high word access) */

/* AUXCTL1 Control Bits */
#define AUX0OK (0x0001u) /* DVCC okay flag. */
#define AUX1OK (0x0002u) /* AUX 1 supply okay flag. */
#define AUX2OK (0x0004u) /* AUX 2 supply okay flag. */
#define AUX2PRIO (0x0008u) /* Auxiliary supply AUX2 priority. */
#define AUX0MD (0x0100u) /* DVCC supply mode. */
#define AUX1MD (0x0200u) /* AUX1 supply mode. */
#define AUX2MD (0x0400u) /* AUX2 supply mode. */

/* AUXCTL1 Control Bits */
#define AUX0OK_L (0x0001u) /* DVCC okay flag. */
#define AUX1OK_L (0x0002u) /* AUX 1 supply okay flag. */
#define AUX2OK_L (0x0004u) /* AUX 2 supply okay flag. */
#define AUX2PRIO_L (0x0008u) /* Auxiliary supply AUX2 priority. */

/* AUXCTL1 Control Bits */
#define AUX0MD_H (0x0001u) /* DVCC supply mode. */
#define AUX1MD_H (0x0002u) /* AUX1 supply mode. */
#define AUX2MD_H (0x0004u) /* AUX2 supply mode. */

/* AUXCTL2 Control Bits */
#define AUX0LVL0 (0x0001u) /* DVCC supply threshold level Bit: 0 */
#define AUX0LVL1 (0x0002u) /* DVCC supply threshold level Bit: 1 */
#define AUX0LVL2 (0x0004u) /* DVCC supply threshold level Bit: 2 */
#define AUX1LVL0 (0x0010u) /* AUX1 supply threshold level Bit: 0 */
#define AUX1LVL1 (0x0020u) /* AUX1 supply threshold level Bit: 1 */
#define AUX1LVL2 (0x0040u) /* AUX1 supply threshold level Bit: 2 */
#define AUX2LVL0 (0x0100u) /* AUX2 supply threshold level Bit: 0 */
#define AUX2LVL1 (0x0200u) /* AUX2 supply threshold level Bit: 1 */
#define AUX2LVL2 (0x0400u) /* AUX2 supply threshold level Bit: 2 */
#define AUXMR0 (0x1000u) /* Auxiliary supply monitoring rate Bit: 0 */
#define AUXMR1 (0x2000u) /* Auxiliary supply monitoring rate Bit: 1 */

/* AUXCTL2 Control Bits */
#define AUX0LVL0_L (0x0001u) /* DVCC supply threshold level Bit: 0 */
#define AUX0LVL1_L (0x0002u) /* DVCC supply threshold level Bit: 1 */
#define AUX0LVL2_L (0x0004u) /* DVCC supply threshold level Bit: 2 */
#define AUX1LVL0_L (0x0010u) /* AUX1 supply threshold level Bit: 0 */
#define AUX1LVL1_L (0x0020u) /* AUX1 supply threshold level Bit: 1 */
#define AUX1LVL2_L (0x0040u) /* AUX1 supply threshold level Bit: 2 */

/* AUXCTL2 Control Bits */
#define AUX2LVL0_H (0x0001u) /* AUX2 supply threshold level Bit: 0 */
#define AUX2LVL1_H (0x0002u) /* AUX2 supply threshold level Bit: 1 */
#define AUX2LVL2_H (0x0004u) /* AUX2 supply threshold level Bit: 2 */
#define AUXMR0_H (0x0010u) /* Auxiliary supply monitoring rate Bit: 0 */
#define AUXMR1_H (0x0020u) /* Auxiliary supply monitoring rate Bit: 1 */

#define AUX0LVL_0 (0x0000u) /* DVCC supply threshold level: 0 */
#define AUX0LVL_1 (0x0001u) /* DVCC supply threshold level: 1 */
#define AUX0LVL_2 (0x0002u) /* DVCC supply threshold level: 2 */
#define AUX0LVL_3 (0x0003u) /* DVCC supply threshold level: 3 */
#define AUX0LVL_4 (0x0004u) /* DVCC supply threshold level: 4 */
#define AUX0LVL_5 (0x0005u) /* DVCC supply threshold level: 5 */
#define AUX0LVL_6 (0x0006u) /* DVCC supply threshold level: 6 */
#define AUX0LVL_7 (0x0007u) /* DVCC supply threshold level: 7 */

#define AUX1LVL_0 (0x0000u) /* AUX1 supply threshold level: 0 */
#define AUX1LVL_1 (0x0010u) /* AUX1 supply threshold level: 1 */
#define AUX1LVL_2 (0x0020u) /* AUX1 supply threshold level: 2 */
#define AUX1LVL_3 (0x0030u) /* AUX1 supply threshold level: 3 */
#define AUX1LVL_4 (0x0040u) /* AUX1 supply threshold level: 4 */
#define AUX1LVL_5 (0x0050u) /* AUX1 supply threshold level: 5 */
#define AUX1LVL_6 (0x0060u) /* AUX1 supply threshold level: 6 */
#define AUX1LVL_7 (0x0070u) /* AUX1 supply threshold level: 7 */

#define AUX2LVL_0 (0x0000u) /* AUX2 supply threshold level: 0 */
#define AUX2LVL_1 (0x0100u) /* AUX2 supply threshold level: 1 */
#define AUX2LVL_2 (0x0200u) /* AUX2 supply threshold level: 2 */
#define AUX2LVL_3 (0x0300u) /* AUX2 supply threshold level: 3 */
#define AUX2LVL_4 (0x0400u) /* AUX2 supply threshold level: 4 */
#define AUX2LVL_5 (0x0500u) /* AUX2 supply threshold level: 5 */
#define AUX2LVL_6 (0x0600u) /* AUX2 supply threshold level: 6 */
#define AUX2LVL_7 (0x0700u) /* AUX2 supply threshold level: 7 */

#define AUXMR_0 (0x0000u) /* Auxiliary supply monitoring rate: 0 */
#define AUXMR_1 (0x1000u) /* Auxiliary supply monitoring rate: 1 */
#define AUXMR_2 (0x2000u) /* Auxiliary supply monitoring rate: 2 */
#define AUXMR_3 (0x3000u) /* Auxiliary supply monitoring rate: 3 */

/* AUXADCCTL Control Bits */
#define AUXADC (0x0001u) /* Auxiliary supplies to ADC */
#define AUXADCSEL0 (0x0002u) /* Select supply to be measured with ADC Bit: 0 */
#define AUXADCSEL1 (0x0004u) /* Select supply to be measured with ADC Bit: 1 */
#define AUXADCR0 (0x0010u) /* Load resistance Bit: 0 */
#define AUXADCR1 (0x0020u) /* Load resistance Bit: 1 */

/* AUXADCCTL Control Bits */
#define AUXADC_L (0x0001u) /* Auxiliary supplies to ADC */
#define AUXADCSEL0_L (0x0002u) /* Select supply to be measured with ADC Bit: 0 */
#define AUXADCSEL1_L (0x0004u) /* Select supply to be measured with ADC Bit: 1 */
#define AUXADCR0_L (0x0010u) /* Load resistance Bit: 0 */
#define AUXADCR1_L (0x0020u) /* Load resistance Bit: 1 */

/* AUXADCCTL Control Bits */

#define AUXADCSEL_0 (0x0000u) /* Select supply to be measured with ADC: DVCC */
#define AUXADCSEL_1 (0x0002u) /* Select supply to be measured with ADC: AUXVCC1 */
#define AUXADCSEL_2 (0x0004u) /* Select supply to be measured with ADC: AUXVCC2 */
#define AUXADCSEL_3 (0x0006u) /* Select supply to be measured with ADC: AUXVCC3 */
#define AUXADCSEL__DVCC (0x0000u) /* Select supply to be measured with ADC: DVCC */
#define AUXADCSEL__AUXVCC1 (0x0002u) /* Select supply to be measured with ADC: AUXVCC1 */
#define AUXADCSEL__AUXVCC2 (0x0004u) /* Select supply to be measured with ADC: AUXVCC2 */
#define AUXADCSEL__AUXVCC3 (0x0006u) /* Select supply to be measured with ADC: AUXVCC3 */

#define AUXADCR_0 (0x0000u) /* Load resistance: 0 */
#define AUXADCR_1 (0x0010u) /* Load resistance: 1 */
#define AUXADCR_2 (0x0020u) /* Load resistance: 2 */
#define AUXADCR_3 (0x0030u) /* Load resistance: 3 */

/* AUXxCHCTL Control Bits */
#define AUXCHEN (0x0001u) /* Lock auxiliary supply system. */
#define AUXCHC0 (0x0002u) /* Charger charge current Bit: 0 */
#define AUXCHC1 (0x0004u) /* Charger charge current Bit: 1 */
#define AUXCHV0 (0x0010u) /* Charger end voltage Bit: 0 */
#define AUXCHV1 (0x0020u) /* Charger end voltage Bit: 1 */

/* AUXxCHCTL Control Bits */
#define AUXCHEN_L (0x0001u) /* Lock auxiliary supply system. */
#define AUXCHC0_L (0x0002u) /* Charger charge current Bit: 0 */
#define AUXCHC1_L (0x0004u) /* Charger charge current Bit: 1 */
#define AUXCHV0_L (0x0010u) /* Charger end voltage Bit: 0 */
#define AUXCHV1_L (0x0020u) /* Charger end voltage Bit: 1 */

/* AUXxCHCTL Control Bits */

#define AUXCHKEY (0x6900u) /* Charger Access Key */

#define AUXCHC_0 (0x0000u) /* Charger charge current: 0 */
#define AUXCHC_1 (0x0002u) /* Charger charge current: 1 */
#define AUXCHC_2 (0x0004u) /* Charger charge current: 2 */
#define AUXCHC_3 (0x0006u) /* Charger charge current: 3 */

#define AUXCHV_0 (0x0000u) /* Charger end voltage: 0 */
#define AUXCHV_1 (0x0010u) /* Charger end voltage: 1 */
#define AUXCHV_2 (0x0020u) /* Charger end voltage: 2 */
#define AUXCHV_3 (0x0030u) /* Charger end voltage: 3 */

/* AUXIFG Control Bits */
#define AUX0SWIFG (0x0001u) /* Switched to DVCC interrupt flag */
#define AUX1SWIFG (0x0002u) /* Switched to AUX1 interrupt flag */
#define AUX2SWIFG (0x0004u) /* Switched to AUX2 interrupt flag */
#define AUX0DRPIFG (0x0010u) /* DVCC dropped below its threshold interrupt flag */
#define AUX1DRPIFG (0x0020u) /* AUX1 dropped below its threshold interrupt flag */
#define AUX2DRPIFG (0x0040u) /* AUX2 dropped below its threshold interrupt flag */
#define AUXMONIFG (0x0080u) /* Supply monitor interrupt flag */
#define AUXSWNMIFG (0x0100u) /* Supplies switched (non-)maskable interrupt flag */

/* AUXIFG Control Bits */
#define AUX0SWIFG_L (0x0001u) /* Switched to DVCC interrupt flag */
#define AUX1SWIFG_L (0x0002u) /* Switched to AUX1 interrupt flag */
#define AUX2SWIFG_L (0x0004u) /* Switched to AUX2 interrupt flag */
#define AUX0DRPIFG_L (0x0010u) /* DVCC dropped below its threshold interrupt flag */
#define AUX1DRPIFG_L (0x0020u) /* AUX1 dropped below its threshold interrupt flag */
#define AUX2DRPIFG_L (0x0040u) /* AUX2 dropped below its threshold interrupt flag */
#define AUXMONIFG_L (0x0080u) /* Supply monitor interrupt flag */

/* AUXIFG Control Bits */
#define AUXSWNMIFG_H (0x0001u) /* Supplies switched (non-)maskable interrupt flag */

/* AUXIE Control Bits */
#define AUX0SWIE (0x0001u) /* Switched to DVCC interrupt enable */
#define AUX1SWIE (0x0002u) /* Switched to AUX1 interrupt enable */
#define AUX2SWIE (0x0004u) /* Switched to AUX2 interrupt enable */
#define AUXSWGIE (0x0008u) /* Global supply switched interrupt enable. */
#define AUX0DRPIE (0x0010u) /* DVCC dropped below its threshold interrupt enable */
#define AUX1DRPIE (0x0020u) /* AUX1 dropped below its threshold interrupt enable */
#define AUX2DRPIE (0x0040u) /* AUX2 dropped below its threshold interrupt enable */
#define AUXMONIE (0x0080u) /* Supply monitor interrupt enable */
#define AUXSWNMIE (0x0100u) /* Supplies switched (non-)maskable interrupt enable */

/* AUXIE Control Bits */
#define AUX0SWIE_L (0x0001u) /* Switched to DVCC interrupt enable */
#define AUX1SWIE_L (0x0002u) /* Switched to AUX1 interrupt enable */
#define AUX2SWIE_L (0x0004u) /* Switched to AUX2 interrupt enable */
#define AUXSWGIE_L (0x0008u) /* Global supply switched interrupt enable. */
#define AUX0DRPIE_L (0x0010u) /* DVCC dropped below its threshold interrupt enable */
#define AUX1DRPIE_L (0x0020u) /* AUX1 dropped below its threshold interrupt enable */
#define AUX2DRPIE_L (0x0040u) /* AUX2 dropped below its threshold interrupt enable */
#define AUXMONIE_L (0x0080u) /* Supply monitor interrupt enable */

/* AUXIE Control Bits */
#define AUXSWNMIE_H (0x0001u) /* Supplies switched (non-)maskable interrupt enable */

/* AUXIV Definitions */
#define AUXIV_NONE (0x0000u) /* No Interrupt pending */
#define AUXIV_AUXSWNMIFG (0x0002u) /* AUXSWNMIFG */
#define AUXIV_AUX0SWIFG (0x0004u) /* AUX0SWIFG */
#define AUXIV_AUX1SWIFG (0x0006u) /* AUX1SWIFG */
#define AUXIV_AUX2SWIFG (0x0008u) /* AUX2SWIFG */
#define AUXIV_AUX0DRPIFG (0x000Au) /* AUX0DRPIFG */
#define AUXIV_AUX1DRPIFG (0x000Cu) /* AUX1DRPIFG */
#define AUXIV_AUX2DRPIFG (0x000Eu) /* AUX2DRPIFG */
#define AUXIV_AUXMONIFG (0x0010u) /* AUXMONIFG */

/*************************************************************
* Backup RAM Module
*************************************************************/
#define __MSP430_HAS_BACKUP_RAM__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_BACKUP_RAM__ 0x0480

#define BAKMEM0_ (0x0480u) /* Battery Backup Memory 0 */
DEFCW( BAKMEM0 , BAKMEM0_)
#define BAKMEM1_ (0x0482u) /* Battery Backup Memory 0 */
DEFCW( BAKMEM1 , BAKMEM1_)
#define BAKMEM2_ (0x0484u) /* Battery Backup Memory 0 */
DEFCW( BAKMEM2 , BAKMEM2_)
#define BAKMEM3_ (0x0486u) /* Battery Backup Memory 0 */
DEFCW( BAKMEM3 , BAKMEM3_)

/*************************************************************
* CRC Module
*************************************************************/
#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_CRC__ 0x0150

#define CRCDI_ (0x0150u) /* CRC Data In Register */
DEFCW( CRCDI , CRCDI_)
#define CRCDIRB_ (0x0152u) /* CRC data in reverse byte Register */
DEFCW( CRCDIRB , CRCDIRB_)
#define CRCINIRES_ (0x0154u) /* CRC Initialisation Register and Result Register */
DEFCW( CRCINIRES , CRCINIRES_)
#define CRCRESR_ (0x0156u) /* CRC reverse result Register */
DEFCW( CRCRESR , CRCRESR_)

/************************************************************
* DMA_X
************************************************************/
#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500

#define DMACTL0_ (0x0500u) /* DMA Module Control 0 */
DEFCW( DMACTL0 , DMACTL0_)
#define DMACTL1_ (0x0502u) /* DMA Module Control 1 */
DEFCW( DMACTL1 , DMACTL1_)
#define DMACTL2_ (0x0504u) /* DMA Module Control 2 */
DEFCW( DMACTL2 , DMACTL2_)
#define DMACTL3_ (0x0506u) /* DMA Module Control 3 */
DEFCW( DMACTL3 , DMACTL3_)
#define DMACTL4_ (0x0508u) /* DMA Module Control 4 */
DEFCW( DMACTL4 , DMACTL4_)
#define DMAIV_ (0x050Eu) /* DMA Interrupt Vector Word */
DEFCW( DMAIV , DMAIV_)

#define DMA0CTL_ (0x0510u) /* DMA Channel 0 Control */
DEFCW( DMA0CTL , DMA0CTL_)
#define DMA0SA_ (0x0512u) /* DMA Channel 0 Source Address */
DEFA( DMA0SA , DMA0SA_)
#define DMA0DA_ (0x0516u) /* DMA Channel 0 Destination Address */
DEFA( DMA0DA , DMA0DA_)
#define DMA0SZ_ (0x051Au) /* DMA Channel 0 Transfer Size */
DEFW( DMA0SZ , DMA0SZ_)

#define DMA1CTL_ (0x0520u) /* DMA Channel 1 Control */
DEFCW( DMA1CTL , DMA1CTL_)
#define DMA1SA_ (0x0522u) /* DMA Channel 1 Source Address */
DEFA( DMA1SA , DMA1SA_)
#define DMA1DA_ (0x0526u) /* DMA Channel 1 Destination Address */
DEFA( DMA1DA , DMA1DA_)
#define DMA1SZ_ (0x052Au) /* DMA Channel 1 Transfer Size */
DEFW( DMA1SZ , DMA1SZ_)

#define DMA2CTL_ (0x0530u) /* DMA Channel 2 Control */
DEFCW( DMA2CTL , DMA2CTL_)
#define DMA2SA_ (0x0532u) /* DMA Channel 2 Source Address */
DEFA( DMA2SA , DMA2SA_)
#define DMA2DA_ (0x0536u) /* DMA Channel 2 Destination Address */
DEFA( DMA2DA , DMA2DA_)
#define DMA2SZ_ (0x053Au) /* DMA Channel 2 Transfer Size */
DEFW( DMA2SZ , DMA2SZ_)

/* DMACTL0 Control Bits */
#define DMA0TSEL0 (0x0001u) /* DMA channel 0 transfer select bit 0 */
#define DMA0TSEL1 (0x0002u) /* DMA channel 0 transfer select bit 1 */
#define DMA0TSEL2 (0x0004u) /* DMA channel 0 transfer select bit 2 */
#define DMA0TSEL3 (0x0008u) /* DMA channel 0 transfer select bit 3 */
#define DMA0TSEL4 (0x0010u) /* DMA channel 0 transfer select bit 4 */
#define DMA1TSEL0 (0x0100u) /* DMA channel 1 transfer select bit 0 */
#define DMA1TSEL1 (0x0200u) /* DMA channel 1 transfer select bit 1 */
#define DMA1TSEL2 (0x0400u) /* DMA channel 1 transfer select bit 2 */
#define DMA1TSEL3 (0x0800u) /* DMA channel 1 transfer select bit 3 */
#define DMA1TSEL4 (0x1000u) /* DMA channel 1 transfer select bit 4 */

/* DMACTL0 Control Bits */
#define DMA0TSEL0_L (0x0001u) /* DMA channel 0 transfer select bit 0 */
#define DMA0TSEL1_L (0x0002u) /* DMA channel 0 transfer select bit 1 */
#define DMA0TSEL2_L (0x0004u) /* DMA channel 0 transfer select bit 2 */
#define DMA0TSEL3_L (0x0008u) /* DMA channel 0 transfer select bit 3 */
#define DMA0TSEL4_L (0x0010u) /* DMA channel 0 transfer select bit 4 */

/* DMACTL0 Control Bits */
#define DMA1TSEL0_H (0x0001u) /* DMA channel 1 transfer select bit 0 */
#define DMA1TSEL1_H (0x0002u) /* DMA channel 1 transfer select bit 1 */
#define DMA1TSEL2_H (0x0004u) /* DMA channel 1 transfer select bit 2 */
#define DMA1TSEL3_H (0x0008u) /* DMA channel 1 transfer select bit 3 */
#define DMA1TSEL4_H (0x0010u) /* DMA channel 1 transfer select bit 4 */

/* DMACTL01 Control Bits */
#define DMA2TSEL0 (0x0001u) /* DMA channel 2 transfer select bit 0 */
#define DMA2TSEL1 (0x0002u) /* DMA channel 2 transfer select bit 1 */
#define DMA2TSEL2 (0x0004u) /* DMA channel 2 transfer select bit 2 */
#define DMA2TSEL3 (0x0008u) /* DMA channel 2 transfer select bit 3 */
#define DMA2TSEL4 (0x0010u) /* DMA channel 2 transfer select bit 4 */

/* DMACTL01 Control Bits */
#define DMA2TSEL0_L (0x0001u) /* DMA channel 2 transfer select bit 0 */
#define DMA2TSEL1_L (0x0002u) /* DMA channel 2 transfer select bit 1 */
#define DMA2TSEL2_L (0x0004u) /* DMA channel 2 transfer select bit 2 */
#define DMA2TSEL3_L (0x0008u) /* DMA channel 2 transfer select bit 3 */
#define DMA2TSEL4_L (0x0010u) /* DMA channel 2 transfer select bit 4 */

/* DMACTL01 Control Bits */

/* DMACTL4 Control Bits */
#define ENNMI (0x0001u) /* Enable NMI interruption of DMA */
#define ROUNDROBIN (0x0002u) /* Round-Robin DMA channel priorities */
#define DMARMWDIS (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */

/* DMACTL4 Control Bits */
#define ENNMI_L (0x0001u) /* Enable NMI interruption of DMA */
#define ROUNDROBIN_L (0x0002u) /* Round-Robin DMA channel priorities */
#define DMARMWDIS_L (0x0004u) /* Inhibited DMA transfers during read-modify-write CPU operations */

/* DMACTL4 Control Bits */

/* DMAxCTL Control Bits */
#define DMAREQ (0x0001u) /* Initiate DMA transfer with DMATSEL */
#define DMAABORT (0x0002u) /* DMA transfer aborted by NMI */
#define DMAIE (0x0004u) /* DMA interrupt enable */
#define DMAIFG (0x0008u) /* DMA interrupt flag */
#define DMAEN (0x0010u) /* DMA enable */
#define DMALEVEL (0x0020u) /* DMA level sensitive trigger select */
#define DMASRCBYTE (0x0040u) /* DMA source byte */
#define DMADSTBYTE (0x0080u) /* DMA destination byte */
#define DMASRCINCR0 (0x0100u) /* DMA source increment bit 0 */
#define DMASRCINCR1 (0x0200u) /* DMA source increment bit 1 */
#define DMADSTINCR0 (0x0400u) /* DMA destination increment bit 0 */
#define DMADSTINCR1 (0x0800u) /* DMA destination increment bit 1 */
#define DMADT0 (0x1000u) /* DMA transfer mode bit 0 */
#define DMADT1 (0x2000u) /* DMA transfer mode bit 1 */
#define DMADT2 (0x4000u) /* DMA transfer mode bit 2 */

/* DMAxCTL Control Bits */
#define DMAREQ_L (0x0001u) /* Initiate DMA transfer with DMATSEL */
#define DMAABORT_L (0x0002u) /* DMA transfer aborted by NMI */
#define DMAIE_L (0x0004u) /* DMA interrupt enable */
#define DMAIFG_L (0x0008u) /* DMA interrupt flag */
#define DMAEN_L (0x0010u) /* DMA enable */
#define DMALEVEL_L (0x0020u) /* DMA level sensitive trigger select */
#define DMASRCBYTE_L (0x0040u) /* DMA source byte */
#define DMADSTBYTE_L (0x0080u) /* DMA destination byte */

/* DMAxCTL Control Bits */
#define DMASRCINCR0_H (0x0001u) /* DMA source increment bit 0 */
#define DMASRCINCR1_H (0x0002u) /* DMA source increment bit 1 */
#define DMADSTINCR0_H (0x0004u) /* DMA destination increment bit 0 */
#define DMADSTINCR1_H (0x0008u) /* DMA destination increment bit 1 */
#define DMADT0_H (0x0010u) /* DMA transfer mode bit 0 */
#define DMADT1_H (0x0020u) /* DMA transfer mode bit 1 */
#define DMADT2_H (0x0040u) /* DMA transfer mode bit 2 */

#define DMASWDW (0*0x0040u) /* DMA transfer: source word to destination word */
#define DMASBDW (1*0x0040u) /* DMA transfer: source byte to destination word */
#define DMASWDB (2*0x0040u) /* DMA transfer: source word to destination byte */
#define DMASBDB (3*0x0040u) /* DMA transfer: source byte to destination byte */

#define DMASRCINCR_0 (0*0x0100u) /* DMA source increment 0: source address unchanged */
#define DMASRCINCR_1 (1*0x0100u) /* DMA source increment 1: source address unchanged */
#define DMASRCINCR_2 (2*0x0100u) /* DMA source increment 2: source address decremented */
#define DMASRCINCR_3 (3*0x0100u) /* DMA source increment 3: source address incremented */

#define DMADSTINCR_0 (0*0x0400u) /* DMA destination increment 0: destination address unchanged */
#define DMADSTINCR_1 (1*0x0400u) /* DMA destination increment 1: destination address unchanged */
#define DMADSTINCR_2 (2*0x0400u) /* DMA destination increment 2: destination address decremented */
#define DMADSTINCR_3 (3*0x0400u) /* DMA destination increment 3: destination address incremented */

#define DMADT_0 (0*0x1000u) /* DMA transfer mode 0: Single transfer */
#define DMADT_1 (1*0x1000u) /* DMA transfer mode 1: Block transfer */
#define DMADT_2 (2*0x1000u) /* DMA transfer mode 2: Burst-Block transfer */
#define DMADT_3 (3*0x1000u) /* DMA transfer mode 3: Burst-Block transfer */
#define DMADT_4 (4*0x1000u) /* DMA transfer mode 4: Repeated Single transfer */
#define DMADT_5 (5*0x1000u) /* DMA transfer mode 5: Repeated Block transfer */
#define DMADT_6 (6*0x1000u) /* DMA transfer mode 6: Repeated Burst-Block transfer */
#define DMADT_7 (7*0x1000u) /* DMA transfer mode 7: Repeated Burst-Block transfer */

/* DMAIV Definitions */
#define DMAIV_NONE (0x0000u) /* No Interrupt pending */
#define DMAIV_DMA0IFG (0x0002u) /* DMA0IFG*/
#define DMAIV_DMA1IFG (0x0004u) /* DMA1IFG*/
#define DMAIV_DMA2IFG (0x0006u) /* DMA2IFG*/

#define DMA0TSEL_0 (0*0x0001u) /* DMA channel 0 transfer select 0 */
#define DMA0TSEL_1 (1*0x0001u) /* DMA channel 0 transfer select 1 */
#define DMA0TSEL_2 (2*0x0001u) /* DMA channel 0 transfer select 2 */
#define DMA0TSEL_3 (3*0x0001u) /* DMA channel 0 transfer select 3 */
#define DMA0TSEL_4 (4*0x0001u) /* DMA channel 0 transfer select 4 */
#define DMA0TSEL_5 (5*0x0001u) /* DMA channel 0 transfer select 5 */
#define DMA0TSEL_6 (6*0x0001u) /* DMA channel 0 transfer select 6 */
#define DMA0TSEL_7 (7*0x0001u) /* DMA channel 0 transfer select 7 */
#define DMA0TSEL_8 (8*0x0001u) /* DMA channel 0 transfer select 8 */
#define DMA0TSEL_9 (9*0x0001u) /* DMA channel 0 transfer select 9 */
#define DMA0TSEL_10 (10*0x0001u) /* DMA channel 0 transfer select 10 */
#define DMA0TSEL_11 (11*0x0001u) /* DMA channel 0 transfer select 11 */
#define DMA0TSEL_12 (12*0x0001u) /* DMA channel 0 transfer select 12 */
#define DMA0TSEL_13 (13*0x0001u) /* DMA channel 0 transfer select 13 */
#define DMA0TSEL_14 (14*0x0001u) /* DMA channel 0 transfer select 14 */
#define DMA0TSEL_15 (15*0x0001u) /* DMA channel 0 transfer select 15 */
#define DMA0TSEL_16 (16*0x0001u) /* DMA channel 0 transfer select 16 */
#define DMA0TSEL_17 (17*0x0001u) /* DMA channel 0 transfer select 17 */
#define DMA0TSEL_18 (18*0x0001u) /* DMA channel 0 transfer select 18 */
#define DMA0TSEL_19 (19*0x0001u) /* DMA channel 0 transfer select 19 */
#define DMA0TSEL_20 (20*0x0001u) /* DMA channel 0 transfer select 20 */
#define DMA0TSEL_21 (21*0x0001u) /* DMA channel 0 transfer select 21 */
#define DMA0TSEL_22 (22*0x0001u) /* DMA channel 0 transfer select 22 */
#define DMA0TSEL_23 (23*0x0001u) /* DMA channel 0 transfer select 23 */
#define DMA0TSEL_24 (24*0x0001u) /* DMA channel 0 transfer select 24 */
#define DMA0TSEL_25 (25*0x0001u) /* DMA channel 0 transfer select 25 */
#define DMA0TSEL_26 (26*0x0001u) /* DMA channel 0 transfer select 26 */
#define DMA0TSEL_27 (27*0x0001u) /* DMA channel 0 transfer select 27 */
#define DMA0TSEL_28 (28*0x0001u) /* DMA channel 0 transfer select 28 */
#define DMA0TSEL_29 (29*0x0001u) /* DMA channel 0 transfer select 29 */
#define DMA0TSEL_30 (30*0x0001u) /* DMA channel 0 transfer select 30 */
#define DMA0TSEL_31 (31*0x0001u) /* DMA channel 0 transfer select 31 */

#define DMA1TSEL_0 (0*0x0100u) /* DMA channel 1 transfer select 0 */
#define DMA1TSEL_1 (1*0x0100u) /* DMA channel 1 transfer select 1 */
#define DMA1TSEL_2 (2*0x0100u) /* DMA channel 1 transfer select 2 */
#define DMA1TSEL_3 (3*0x0100u) /* DMA channel 1 transfer select 3 */
#define DMA1TSEL_4 (4*0x0100u) /* DMA channel 1 transfer select 4 */
#define DMA1TSEL_5 (5*0x0100u) /* DMA channel 1 transfer select 5 */
#define DMA1TSEL_6 (6*0x0100u) /* DMA channel 1 transfer select 6 */
#define DMA1TSEL_7 (7*0x0001u) /* DMA channel 1 transfer select 7 */
#define DMA1TSEL_8 (8*0x0001u) /* DMA channel 1 transfer select 8 */
#define DMA1TSEL_9 (9*0x0100u) /* DMA channel 1 transfer select 9 */
#define DMA1TSEL_10 (10*0x0100u) /* DMA channel 1 transfer select 10 */
#define DMA1TSEL_11 (11*0x0100u) /* DMA channel 1 transfer select 11 */
#define DMA1TSEL_12 (12*0x0100u) /* DMA channel 1 transfer select 12 */
#define DMA1TSEL_13 (13*0x0100u) /* DMA channel 1 transfer select 13 */
#define DMA1TSEL_14 (14*0x0100u) /* DMA channel 1 transfer select 14 */
#define DMA1TSEL_15 (15*0x0100u) /* DMA channel 1 transfer select 15 */
#define DMA1TSEL_16 (16*0x0100u) /* DMA channel 1 transfer select 16 */
#define DMA1TSEL_17 (17*0x0100u) /* DMA channel 1 transfer select 17 */
#define DMA1TSEL_18 (18*0x0100u) /* DMA channel 1 transfer select 18 */
#define DMA1TSEL_19 (19*0x0100u) /* DMA channel 1 transfer select 19 */
#define DMA1TSEL_20 (20*0x0100u) /* DMA channel 1 transfer select 20 */
#define DMA1TSEL_21 (21*0x0100u) /* DMA channel 1 transfer select 21 */
#define DMA1TSEL_22 (22*0x0100u) /* DMA channel 1 transfer select 22 */
#define DMA1TSEL_23 (23*0x0100u) /* DMA channel 1 transfer select 23 */
#define DMA1TSEL_24 (24*0x0100u) /* DMA channel 1 transfer select 24 */
#define DMA1TSEL_25 (25*0x0100u) /* DMA channel 1 transfer select 25 */
#define DMA1TSEL_26 (26*0x0100u) /* DMA channel 1 transfer select 26 */
#define DMA1TSEL_27 (27*0x0100u) /* DMA channel 1 transfer select 27 */
#define DMA1TSEL_28 (28*0x0100u) /* DMA channel 1 transfer select 28 */
#define DMA1TSEL_29 (29*0x0100u) /* DMA channel 1 transfer select 29 */
#define DMA1TSEL_30 (30*0x0100u) /* DMA channel 1 transfer select 30 */
#define DMA1TSEL_31 (31*0x0100u) /* DMA channel 1 transfer select 31 */

#define DMA2TSEL_0 (0*0x0001u) /* DMA channel 2 transfer select 0 */
#define DMA2TSEL_1 (1*0x0001u) /* DMA channel 2 transfer select 1 */
#define DMA2TSEL_2 (2*0x0001u) /* DMA channel 2 transfer select 2 */
#define DMA2TSEL_3 (3*0x0001u) /* DMA channel 2 transfer select 3 */
#define DMA2TSEL_4 (4*0x0001u) /* DMA channel 2 transfer select 4 */
#define DMA2TSEL_5 (5*0x0001u) /* DMA channel 2 transfer select 5 */
#define DMA2TSEL_6 (6*0x0001u) /* DMA channel 2 transfer select 6 */
#define DMA2TSEL_7 (7*0x0001u) /* DMA channel 2 transfer select 7 */
#define DMA2TSEL_8 (8*0x0001u) /* DMA channel 2 transfer select 8 */
#define DMA2TSEL_9 (9*0x0001u) /* DMA channel 2 transfer select 9 */
#define DMA2TSEL_10 (10*0x0001u) /* DMA channel 2 transfer select 10 */
#define DMA2TSEL_11 (11*0x0001u) /* DMA channel 2 transfer select 11 */
#define DMA2TSEL_12 (12*0x0001u) /* DMA channel 2 transfer select 12 */
#define DMA2TSEL_13 (13*0x0001u) /* DMA channel 2 transfer select 13 */
#define DMA2TSEL_14 (14*0x0001u) /* DMA channel 2 transfer select 14 */
#define DMA2TSEL_15 (15*0x0001u) /* DMA channel 2 transfer select 15 */
#define DMA2TSEL_16 (16*0x0001u) /* DMA channel 2 transfer select 16 */
#define DMA2TSEL_17 (17*0x0001u) /* DMA channel 2 transfer select 17 */
#define DMA2TSEL_18 (18*0x0001u) /* DMA channel 2 transfer select 18 */
#define DMA2TSEL_19 (19*0x0001u) /* DMA channel 2 transfer select 19 */
#define DMA2TSEL_20 (20*0x0001u) /* DMA channel 2 transfer select 20 */
#define DMA2TSEL_21 (21*0x0001u) /* DMA channel 2 transfer select 21 */
#define DMA2TSEL_22 (22*0x0001u) /* DMA channel 2 transfer select 22 */
#define DMA2TSEL_23 (23*0x0001u) /* DMA channel 2 transfer select 23 */
#define DMA2TSEL_24 (24*0x0001u) /* DMA channel 2 transfer select 24 */
#define DMA2TSEL_25 (25*0x0001u) /* DMA channel 2 transfer select 25 */
#define DMA2TSEL_26 (26*0x0001u) /* DMA channel 2 transfer select 26 */
#define DMA2TSEL_27 (27*0x0001u) /* DMA channel 2 transfer select 27 */
#define DMA2TSEL_28 (28*0x0001u) /* DMA channel 2 transfer select 28 */
#define DMA2TSEL_29 (29*0x0001u) /* DMA channel 2 transfer select 29 */
#define DMA2TSEL_30 (30*0x0001u) /* DMA channel 2 transfer select 30 */
#define DMA2TSEL_31 (31*0x0001u) /* DMA channel 2 transfer select 31 */

#define DMA0TSEL__DMA_REQ (0*0x0001u) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
#define DMA0TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 0 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA0TSEL__TA0CCR1 (2*0x0001u) /* DMA channel 0 transfer select 2: Timer0_A (TA0CCR1.IFG) */
#define DMA0TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 0 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA0TSEL__RES4 (4*0x0001u) /* DMA channel 0 transfer select 4: Reserved */
#define DMA0TSEL__TA2CCR0 (5*0x0001u) /* DMA channel 0 transfer select 5: Timer2_A (TA2CCR0.IFG) */
#define DMA0TSEL__RES6 (6*0x0001u) /* DMA channel 0 transfer select 6: Reserved */
#define DMA0TSEL__TA3CCR0 (7*0x0001u) /* DMA channel 0 transfer select 7: Timer3_A (TA3CCR0.IFG) */
#define DMA0TSEL__RES8 (8*0x0001u) /* DMA channel 0 transfer select 8: Reserved */
#define DMA0TSEL__RES9 (9*0x0001u) /* DMA channel 0 transfer select 9: Reserved */
#define DMA0TSEL__RES10 (10*0x0001u) /* DMA channel 0 transfer select 10: Reserved */
#define DMA0TSEL__RES11 (11*0x0001u) /* DMA channel 0 transfer select 11: Reserved */
#define DMA0TSEL__RES12 (12*0x0001u) /* DMA channel 0 transfer select 12: Reserved */
#define DMA0TSEL__SD24IFG (13*0x0001u) /* DMA channel 0 transfer select 13: SD24IFG */
#define DMA0TSEL__RES14 (14*0x0001u) /* DMA channel 0 transfer select 14: Reserved */
#define DMA0TSEL__RES15 (15*0x0001u) /* DMA channel 0 transfer select 15: Reserved */
#define DMA0TSEL__USCIA0RX (16*0x0001u) /* DMA channel 0 transfer select 16: USCIA0 receive */
#define DMA0TSEL__USCIA0TX (17*0x0001u) /* DMA channel 0 transfer select 17: USCIA0 transmit */
#define DMA0TSEL__USCIA1RX (18*0x0001u) /* DMA channel 0 transfer select 18: USCIA1 receive */
#define DMA0TSEL__USCIA1TX (19*0x0001u) /* DMA channel 0 transfer select 19: USCIA1 transmit */
#define DMA0TSEL__USCIA2RX (20*0x0001u) /* DMA channel 0 transfer select 20: USCIA2 receive */
#define DMA0TSEL__USCIA2TX (21*0x0001u) /* DMA channel 0 transfer select 21: USCIA2 transmit */
#define DMA0TSEL__USCIB0RX (22*0x0001u) /* DMA channel 0 transfer select 22: USCIB0 receive */
#define DMA0TSEL__USCIB0TX (23*0x0001u) /* DMA channel 0 transfer select 23: USCIB0 transmit */
#define DMA0TSEL__ADC10IFG0 (24*0x0001u) /* DMA channel 0 transfer select 24: ADC10IFG0 */
#define DMA0TSEL__RES25 (25*0x0001u) /* DMA channel 0 transfer select 25: Reserved */
#define DMA0TSEL__RES26 (26*0x0001u) /* DMA channel 0 transfer select 26: Reserved */
#define DMA0TSEL__RES27 (27*0x0001u) /* DMA channel 0 transfer select 27: Reserved */
#define DMA0TSEL__RES28 (28*0x0001u) /* DMA channel 0 transfer select 28: Reserved */
#define DMA0TSEL__MPY (29*0x0001u) /* DMA channel 0 transfer select 29: Multiplier ready */
#define DMA0TSEL__DMA2IFG (30*0x0001u) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
#define DMA0TSEL__DMAE0 (31*0x0001u) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */

#define DMA1TSEL__DMA_REQ (0*0x0100u) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
#define DMA1TSEL__TA0CCR0 (1*0x0100u) /* DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA1TSEL__TA0CCR1 (2*0x0100u) /* DMA channel 1 transfer select 2: Timer0_A (TA0CCR1.IFG) */
#define DMA1TSEL__TA1CCR0 (3*0x0100u) /* DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA1TSEL__RES4 (4*0x0100u) /* DMA channel 1 transfer select 4: Reserved */
#define DMA1TSEL__TA2CCR0 (5*0x0100u) /* DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG) */
#define DMA1TSEL__RES6 (6*0x0100u) /* DMA channel 1 transfer select 6: Reserved */
#define DMA1TSEL__TA3CCR0 (7*0x0001u) /* DMA channel 1 transfer select 7: Timer3_A (TA3CCR0.IFG) */
#define DMA1TSEL__RES8 (8*0x0001u) /* DMA channel 1 transfer select 8: Reserved */
#define DMA1TSEL__RES9 (9*0x0100u) /* DMA channel 1 transfer select 9: Reserved */
#define DMA1TSEL__RES10 (10*0x0100u) /* DMA channel 1 transfer select 10: Reserved */
#define DMA1TSEL__RES11 (11*0x0100u) /* DMA channel 1 transfer select 11: Reserved */
#define DMA1TSEL__RES12 (12*0x0100u) /* DMA channel 1 transfer select 12: Reserved */
#define DMA1TSEL__SD24IFG (13*0x0100u) /* DMA channel 1 transfer select 13: SD24IFG */
#define DMA1TSEL__RES14 (14*0x0100u) /* DMA channel 1 transfer select 14: Reserved */
#define DMA1TSEL__RES15 (15*0x0100u) /* DMA channel 1 transfer select 15: Reserved */
#define DMA1TSEL__USCIA0RX (16*0x0100u) /* DMA channel 1 transfer select 16: USCIA0 receive */
#define DMA1TSEL__USCIA0TX (17*0x0100u) /* DMA channel 1 transfer select 17: USCIA0 transmit */
#define DMA1TSEL__USCIA1RX (18*0x0100u) /* DMA channel 1 transfer select 18: USCIA1 receive */
#define DMA1TSEL__USCIA1TX (19*0x0100u) /* DMA channel 1 transfer select 19: USCIA1 transmit */
#define DMA1TSEL__USCIA2RX (20*0x0100u) /* DMA channel 1 transfer select 20: USCIA2 receive */
#define DMA1TSEL__USCIA2TX (21*0x0100u) /* DMA channel 1 transfer select 21: USCIA2 transmit */
#define DMA1TSEL__USCIB0RX (22*0x0100u) /* DMA channel 1 transfer select 22: USCIB0 receive */
#define DMA1TSEL__USCIB0TX (23*0x0100u) /* DMA channel 1 transfer select 23: USCIB0 transmit */
#define DMA1TSEL__ADC10IFG0 (24*0x0100u) /* DMA channel 1 transfer select 24: ADC10IFG0 */
#define DMA1TSEL__RES25 (25*0x0100u) /* DMA channel 1 transfer select 25: Reserved */
#define DMA1TSEL__RES26 (26*0x0100u) /* DMA channel 1 transfer select 26: Reserved */
#define DMA1TSEL__RES27 (27*0x0100u) /* DMA channel 1 transfer select 27: Reserved */
#define DMA1TSEL__RES28 (28*0x0100u) /* DMA channel 1 transfer select 28: Reserved */
#define DMA1TSEL__MPY (29*0x0100u) /* DMA channel 1 transfer select 29: Multiplier ready */
#define DMA1TSEL__DMA0IFG (30*0x0100u) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
#define DMA1TSEL__DMAE0 (31*0x0100u) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */

#define DMA2TSEL__DMA_REQ (0*0x0001u) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
#define DMA2TSEL__TA0CCR0 (1*0x0001u) /* DMA channel 2 transfer select 1: Timer0_A (TA0CCR0.IFG) */
#define DMA2TSEL__TA0CCR1 (2*0x0001u) /* DMA channel 2 transfer select 2: Timer0_A (TA0CCR1.IFG) */
#define DMA2TSEL__TA1CCR0 (3*0x0001u) /* DMA channel 2 transfer select 3: Timer1_A (TA1CCR0.IFG) */
#define DMA2TSEL__RES4 (4*0x0001u) /* DMA channel 2 transfer select 4: Reserved */
#define DMA2TSEL__TA2CCR0 (5*0x0001u) /* DMA channel 2 transfer select 5: Timer2_A (TA2CCR0.IFG) */
#define DMA2TSEL__RES6 (6*0x0001u) /* DMA channel 2 transfer select 6: Reserved */
#define DMA2TSEL__TA3CCR0 (7*0x0001u) /* DMA channel 2 transfer select 7: Timer3_A (TA3CCR0.IFG) */
#define DMA2TSEL__RES8 (8*0x0001u) /* DMA channel 2 transfer select 8: Reserved */
#define DMA2TSEL__RES9 (9*0x0001u) /* DMA channel 2 transfer select 9: Reserved */
#define DMA2TSEL__RES10 (10*0x0001u) /* DMA channel 2 transfer select 10: Reserved */
#define DMA2TSEL__RES11 (11*0x0001u) /* DMA channel 2 transfer select 11: Reserved */
#define DMA2TSEL__RES12 (12*0x0001u) /* DMA channel 2 transfer select 12: Reserved */
#define DMA2TSEL__SD24IFG (13*0x0001u) /* DMA channel 2 transfer select 13: SD24IFG */
#define DMA2TSEL__RES14 (14*0x0001u) /* DMA channel 2 transfer select 14: Reserved */
#define DMA2TSEL__RES15 (15*0x0001u) /* DMA channel 2 transfer select 15: Reserved */
#define DMA2TSEL__USCIA0RX (16*0x0001u) /* DMA channel 2 transfer select 16: USCIA0 receive */
#define DMA2TSEL__USCIA0TX (17*0x0001u) /* DMA channel 2 transfer select 17: USCIA0 transmit */
#define DMA2TSEL__USCIA1RX (18*0x0001u) /* DMA channel 2 transfer select 18: USCIA1 receive */
#define DMA2TSEL__USCIA1TX (19*0x0001u) /* DMA channel 2 transfer select 19: USCIA1 transmit */
#define DMA2TSEL__USCIA2RX (20*0x0001u) /* DMA channel 2 transfer select 20: USCIA2 receive */
#define DMA2TSEL__USCIA2TX (21*0x0001u) /* DMA channel 2 transfer select 21: USCIA2 transmit */
#define DMA2TSEL__USCIB0RX (22*0x0001u) /* DMA channel 2 transfer select 22: USCIB0 receive */
#define DMA2TSEL__USCIB0TX (23*0x0001u) /* DMA channel 2 transfer select 23: USCIB0 transmit */
#define DMA2TSEL__ADC10IFG0 (24*0x0001u) /* DMA channel 2 transfer select 24: ADC10IFG0 */
#define DMA2TSEL__RES25 (25*0x0001u) /* DMA channel 2 transfer select 25: Reserved */
#define DMA2TSEL__RES26 (26*0x0001u) /* DMA channel 2 transfer select 26: Reserved */
#define DMA2TSEL__RES27 (27*0x0001u) /* DMA channel 2 transfer select 27: Reserved */
#define DMA2TSEL__RES28 (28*0x0001u) /* DMA channel 2 transfer select 28: Reserved */
#define DMA2TSEL__MPY (29*0x0001u) /* DMA channel 2 transfer select 29: Multiplier ready */
#define DMA2TSEL__DMA1IFG (30*0x0001u) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
#define DMA2TSEL__DMAE0 (31*0x0001u) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */

/*************************************************************
* Flash Memory
*************************************************************/
#define __MSP430_HAS_FLASH__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_FLASH__ 0x0140

#define FCTL1_ (0x0140u) /* FLASH Control 1 */
DEFCW( FCTL1 , FCTL1_)
//sfrbw FCTL2 (0x0142) /* FLASH Control 2 */
#define FCTL3_ (0x0144u) /* FLASH Control 3 */
DEFCW( FCTL3 , FCTL3_)
#define FCTL4_ (0x0146u) /* FLASH Control 4 */
DEFCW( FCTL4 , FCTL4_)

#define FRPW (0x9600u) /* Flash password returned by read */
#define FWPW (0xA500u) /* Flash password for write */
#define FXPW (0x3300u) /* for use with XOR instruction */
#define FRKEY (0x9600u) /* (legacy definition) Flash key returned by read */
#define FWKEY (0xA500u) /* (legacy definition) Flash key for write */
#define FXKEY (0x3300u) /* (legacy definition) for use with XOR instruction */

/* FCTL1 Control Bits */
//#define RESERVED (0x0001u) /* Reserved */
#define ERASE (0x0002u) /* Enable bit for Flash segment erase */
#define MERAS (0x0004u) /* Enable bit for Flash mass erase */
//#define RESERVED (0x0008u) /* Reserved */
//#define RESERVED (0x0010u) /* Reserved */
#define SWRT (0x0020u) /* Smart Write enable */
#define WRT (0x0040u) /* Enable bit for Flash write */
#define BLKWRT (0x0080u) /* Enable bit for Flash segment write */

/* FCTL1 Control Bits */
//#define RESERVED (0x0001u) /* Reserved */
#define ERASE_L (0x0002u) /* Enable bit for Flash segment erase */
#define MERAS_L (0x0004u) /* Enable bit for Flash mass erase */
//#define RESERVED (0x0008u) /* Reserved */
//#define RESERVED (0x0010u) /* Reserved */
#define SWRT_L (0x0020u) /* Smart Write enable */
#define WRT_L (0x0040u) /* Enable bit for Flash write */
#define BLKWRT_L (0x0080u) /* Enable bit for Flash segment write */

/* FCTL1 Control Bits */
//#define RESERVED (0x0001u) /* Reserved */
//#define RESERVED (0x0008u) /* Reserved */
//#define RESERVED (0x0010u) /* Reserved */

/* FCTL3 Control Bits */
#define BUSY (0x0001u) /* Flash busy: 1 */
#define KEYV (0x0002u) /* Flash Key violation flag */
#define ACCVIFG (0x0004u) /* Flash Access violation flag */
#define WAIT (0x0008u) /* Wait flag for segment write */
#define LOCK (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX (0x0020u) /* Flash Emergency Exit */
#define LOCKA (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
//#define RESERVED (0x0080u) /* Reserved */

/* FCTL3 Control Bits */
#define BUSY_L (0x0001u) /* Flash busy: 1 */
#define KEYV_L (0x0002u) /* Flash Key violation flag */
#define ACCVIFG_L (0x0004u) /* Flash Access violation flag */
#define WAIT_L (0x0008u) /* Wait flag for segment write */
#define LOCK_L (0x0010u) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX_L (0x0020u) /* Flash Emergency Exit */
#define LOCKA_L (0x0040u) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
//#define RESERVED (0x0080u) /* Reserved */

/* FCTL3 Control Bits */
//#define RESERVED (0x0080u) /* Reserved */

/* FCTL4 Control Bits */
#define VPE (0x0001u) /* Voltage Changed during Program Error Flag */
#define MGR0 (0x0010u) /* Marginal read 0 mode. */
#define MGR1 (0x0020u) /* Marginal read 1 mode. */
#define LOCKINFO (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */

/* FCTL4 Control Bits */
#define VPE_L (0x0001u) /* Voltage Changed during Program Error Flag */
#define MGR0_L (0x0010u) /* Marginal read 0 mode. */
#define MGR1_L (0x0020u) /* Marginal read 1 mode. */
#define LOCKINFO_L (0x0080u) /* Lock INFO Memory bit: read = 1 - Segment is locked (read only) */

/* FCTL4 Control Bits */

/************************************************************
* LCD_C
************************************************************/
#define __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_LCD_C__ 0x0A00

#define LCDCCTL0_ (0x0A00u) /* LCD_C Control Register 0 */
DEFCW( LCDCCTL0 , LCDCCTL0_)
#define LCDCCTL1_ (0x0A02u) /* LCD_C Control Register 1 */
DEFCW( LCDCCTL1 , LCDCCTL1_)
#define LCDCBLKCTL_ (0x0A04u) /* LCD_C blinking control register */
DEFCW( LCDCBLKCTL , LCDCBLKCTL_)
#define LCDCMEMCTL_ (0x0A06u) /* LCD_C memory control register */
DEFCW( LCDCMEMCTL , LCDCMEMCTL_)
#define LCDCVCTL_ (0x0A08u) /* LCD_C Voltage Control Register */
DEFCW( LCDCVCTL , LCDCVCTL_)
#define LCDCPCTL0_ (0x0A0Au) /* LCD_C Port Control Register 0 */
DEFCW( LCDCPCTL0 , LCDCPCTL0_)
#define LCDCPCTL1_ (0x0A0Cu) /* LCD_C Port Control Register 1 */
DEFCW( LCDCPCTL1 , LCDCPCTL1_)
#define LCDCPCTL2_ (0x0A0Eu) /* LCD_C Port Control Register 2 */
DEFCW( LCDCPCTL2 , LCDCPCTL2_)
#define LCDCCPCTL_ (0x0A12u) /* LCD_C Charge Pump Control Register 3 */
DEFCW( LCDCCPCTL , LCDCCPCTL_)
#define LCDCIV_ (0x0A1Eu) /* LCD_C Interrupt Vector Register */
DEFW( LCDCIV , LCDCIV_)

// LCDCCTL0
#define LCDON (0x0001u) /* LCD_C LCD On */
#define LCDLP (0x0002u) /* LCD_C Low Power Waveform */
#define LCDSON (0x0004u) /* LCD_C LCD Segments On */
#define LCDMX0 (0x0008u) /* LCD_C Mux Rate Bit: 0 */
#define LCDMX1 (0x0010u) /* LCD_C Mux Rate Bit: 1 */
#define LCDMX2 (0x0020u) /* LCD_C Mux Rate Bit: 2 */
//#define RESERVED (0x0040u) /* LCD_C RESERVED */
#define LCDSSEL (0x0080u) /* LCD_C Clock Select */
#define LCDPRE0 (0x0100u) /* LCD_C LCD frequency pre-scaler Bit: 0 */
#define LCDPRE1 (0x0200u) /* LCD_C LCD frequency pre-scaler Bit: 1 */
#define LCDPRE2 (0x0400u) /* LCD_C LCD frequency pre-scaler Bit: 2 */
#define LCDDIV0 (0x0800u) /* LCD_C LCD frequency divider Bit: 0 */
#define LCDDIV1 (0x1000u) /* LCD_C LCD frequency divider Bit: 1 */
#define LCDDIV2 (0x2000u) /* LCD_C LCD frequency divider Bit: 2 */
#define LCDDIV3 (0x4000u) /* LCD_C LCD frequency divider Bit: 3 */
#define LCDDIV4 (0x8000u) /* LCD_C LCD frequency divider Bit: 4 */

// LCDCCTL0
#define LCDON_L (0x0001u) /* LCD_C LCD On */
#define LCDLP_L (0x0002u) /* LCD_C Low Power Waveform */
#define LCDSON_L (0x0004u) /* LCD_C LCD Segments On */
#define LCDMX0_L (0x0008u) /* LCD_C Mux Rate Bit: 0 */
#define LCDMX1_L (0x0010u) /* LCD_C Mux Rate Bit: 1 */
#define LCDMX2_L (0x0020u) /* LCD_C Mux Rate Bit: 2 */
//#define RESERVED (0x0040u) /* LCD_C RESERVED */
#define LCDSSEL_L (0x0080u) /* LCD_C Clock Select */

// LCDCCTL0
//#define RESERVED (0x0040u) /* LCD_C RESERVED */
#define LCDPRE0_H (0x0001u) /* LCD_C LCD frequency pre-scaler Bit: 0 */
#define LCDPRE1_H (0x0002u) /* LCD_C LCD frequency pre-scaler Bit: 1 */
#define LCDPRE2_H (0x0004u) /* LCD_C LCD frequency pre-scaler Bit: 2 */
#define LCDDIV0_H (0x0008u) /* LCD_C LCD frequency divider Bit: 0 */
#define LCDDIV1_H (0x0010u) /* LCD_C LCD frequency divider Bit: 1 */
#define LCDDIV2_H (0x0020u) /* LCD_C LCD frequency divider Bit: 2 */
#define LCDDIV3_H (0x0040u) /* LCD_C LCD frequency divider Bit: 3 */
#define LCDDIV4_H (0x0080u) /* LCD_C LCD frequency divider Bit: 4 */

#define LCDPRE_0 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */
#define LCDPRE_1 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */
#define LCDPRE_2 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */
#define LCDPRE_3 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */
#define LCDPRE_4 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */
#define LCDPRE_5 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */
#define LCDPRE__1 (0x0000u) /* LCD_C LCD frequency pre-scaler: /1 */
#define LCDPRE__2 (0x0100u) /* LCD_C LCD frequency pre-scaler: /2 */
#define LCDPRE__4 (0x0200u) /* LCD_C LCD frequency pre-scaler: /4 */
#define LCDPRE__8 (0x0300u) /* LCD_C LCD frequency pre-scaler: /8 */
#define LCDPRE__16 (0x0400u) /* LCD_C LCD frequency pre-scaler: /16 */
#define LCDPRE__32 (0x0500u) /* LCD_C LCD frequency pre-scaler: /32 */

#define LCDDIV_0 (0x0000u) /* LCD_C LCD frequency divider: /1 */
#define LCDDIV_1 (0x0800u) /* LCD_C LCD frequency divider: /2 */
#define LCDDIV_2 (0x1000u) /* LCD_C LCD frequency divider: /3 */
#define LCDDIV_3 (0x1800u) /* LCD_C LCD frequency divider: /4 */
#define LCDDIV_4 (0x2000u) /* LCD_C LCD frequency divider: /5 */
#define LCDDIV_5 (0x2800u) /* LCD_C LCD frequency divider: /6 */
#define LCDDIV_6 (0x3000u) /* LCD_C LCD frequency divider: /7 */
#define LCDDIV_7 (0x3800u) /* LCD_C LCD frequency divider: /8 */
#define LCDDIV_8 (0x4000u) /* LCD_C LCD frequency divider: /9 */
#define LCDDIV_9 (0x4800u) /* LCD_C LCD frequency divider: /10 */
#define LCDDIV_10 (0x5000u) /* LCD_C LCD frequency divider: /11 */
#define LCDDIV_11 (0x5800u) /* LCD_C LCD frequency divider: /12 */
#define LCDDIV_12 (0x6000u) /* LCD_C LCD frequency divider: /13 */
#define LCDDIV_13 (0x6800u) /* LCD_C LCD frequency divider: /14 */
#define LCDDIV_14 (0x7000u) /* LCD_C LCD frequency divider: /15 */
#define LCDDIV_15 (0x7800u) /* LCD_C LCD frequency divider: /16 */
#define LCDDIV_16 (0x8000u) /* LCD_C LCD frequency divider: /17 */
#define LCDDIV_17 (0x8800u) /* LCD_C LCD frequency divider: /18 */
#define LCDDIV_18 (0x9000u) /* LCD_C LCD frequency divider: /19 */
#define LCDDIV_19 (0x9800u) /* LCD_C LCD frequency divider: /20 */
#define LCDDIV_20 (0xA000u) /* LCD_C LCD frequency divider: /21 */
#define LCDDIV_21 (0xA800u) /* LCD_C LCD frequency divider: /22 */
#define LCDDIV_22 (0xB000u) /* LCD_C LCD frequency divider: /23 */
#define LCDDIV_23 (0xB800u) /* LCD_C LCD frequency divider: /24 */
#define LCDDIV_24 (0xC000u) /* LCD_C LCD frequency divider: /25 */
#define LCDDIV_25 (0xC800u) /* LCD_C LCD frequency divider: /26 */
#define LCDDIV_26 (0xD000u) /* LCD_C LCD frequency divider: /27 */
#define LCDDIV_27 (0xD800u) /* LCD_C LCD frequency divider: /28 */
#define LCDDIV_28 (0xE000u) /* LCD_C LCD frequency divider: /29 */
#define LCDDIV_29 (0xE800u) /* LCD_C LCD frequency divider: /30 */
#define LCDDIV_30 (0xF000u) /* LCD_C LCD frequency divider: /31 */
#define LCDDIV_31 (0xF800u) /* LCD_C LCD frequency divider: /32 */
#define LCDDIV__1 (0x0000u) /* LCD_C LCD frequency divider: /1 */
#define LCDDIV__2 (0x0800u) /* LCD_C LCD frequency divider: /2 */
#define LCDDIV__3 (0x1000u) /* LCD_C LCD frequency divider: /3 */
#define LCDDIV__4 (0x1800u) /* LCD_C LCD frequency divider: /4 */
#define LCDDIV__5 (0x2000u) /* LCD_C LCD frequency divider: /5 */
#define LCDDIV__6 (0x2800u) /* LCD_C LCD frequency divider: /6 */
#define LCDDIV__7 (0x3000u) /* LCD_C LCD frequency divider: /7 */
#define LCDDIV__8 (0x3800u) /* LCD_C LCD frequency divider: /8 */
#define LCDDIV__9 (0x4000u) /* LCD_C LCD frequency divider: /9 */
#define LCDDIV__10 (0x4800u) /* LCD_C LCD frequency divider: /10 */
#define LCDDIV__11 (0x5000u) /* LCD_C LCD frequency divider: /11 */
#define LCDDIV__12 (0x5800u) /* LCD_C LCD frequency divider: /12 */
#define LCDDIV__13 (0x6000u) /* LCD_C LCD frequency divider: /13 */
#define LCDDIV__14 (0x6800u) /* LCD_C LCD frequency divider: /14 */
#define LCDDIV__15 (0x7000u) /* LCD_C LCD frequency divider: /15 */
#define LCDDIV__16 (0x7800u) /* LCD_C LCD frequency divider: /16 */
#define LCDDIV__17 (0x8000u) /* LCD_C LCD frequency divider: /17 */
#define LCDDIV__18 (0x8800u) /* LCD_C LCD frequency divider: /18 */
#define LCDDIV__19 (0x9000u) /* LCD_C LCD frequency divider: /19 */
#define LCDDIV__20 (0x9800u) /* LCD_C LCD frequency divider: /20 */
#define LCDDIV__21 (0xA000u) /* LCD_C LCD frequency divider: /21 */
#define LCDDIV__22 (0xA800u) /* LCD_C LCD frequency divider: /22 */
#define LCDDIV__23 (0xB000u) /* LCD_C LCD frequency divider: /23 */
#define LCDDIV__24 (0xB800u) /* LCD_C LCD frequency divider: /24 */
#define LCDDIV__25 (0xC000u) /* LCD_C LCD frequency divider: /25 */
#define LCDDIV__26 (0xC800u) /* LCD_C LCD frequency divider: /26 */
#define LCDDIV__27 (0xD000u) /* LCD_C LCD frequency divider: /27 */
#define LCDDIV__28 (0xD800u) /* LCD_C LCD frequency divider: /28 */
#define LCDDIV__29 (0xE000u) /* LCD_C LCD frequency divider: /29 */
#define LCDDIV__30 (0xE800u) /* LCD_C LCD frequency divider: /30 */
#define LCDDIV__31 (0xF000u) /* LCD_C LCD frequency divider: /31 */
#define LCDDIV__32 (0xF800u) /* LCD_C LCD frequency divider: /32 */

/* Display modes coded with Bits 2-4 */
#define LCDSTATIC (LCDSON)
#define LCD2MUX (LCDMX0+LCDSON)
#define LCD3MUX (LCDMX1+LCDSON)
#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
#define LCD5MUX (LCDMX2+LCDSON)
#define LCD6MUX (LCDMX2+LCDMX0+LCDSON)
#define LCD7MUX (LCDMX2+LCDMX1+LCDSON)
#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)

// LCDCCTL1
#define LCDFRMIFG (0x0001u) /* LCD_C LCD frame interrupt flag */
#define LCDBLKOFFIFG (0x0002u) /* LCD_C LCD blinking off interrupt flag, */
#define LCDBLKONIFG (0x0004u) /* LCD_C LCD blinking on interrupt flag, */
#define LCDNOCAPIFG (0x0008u) /* LCD_C No cpacitance connected interrupt flag */
#define LCDFRMIE (0x0100u) /* LCD_C LCD frame interrupt enable */
#define LCDBLKOFFIE (0x0200u) /* LCD_C LCD blinking off interrupt flag, */
#define LCDBLKONIE (0x0400u) /* LCD_C LCD blinking on interrupt flag, */
#define LCDNOCAPIE (0x0800u) /* LCD_C No cpacitance connected interrupt enable */

// LCDCCTL1
#define LCDFRMIFG_L (0x0001u) /* LCD_C LCD frame interrupt flag */
#define LCDBLKOFFIFG_L (0x0002u) /* LCD_C LCD blinking off interrupt flag, */
#define LCDBLKONIFG_L (0x0004u) /* LCD_C LCD blinking on interrupt flag, */
#define LCDNOCAPIFG_L (0x0008u) /* LCD_C No cpacitance connected interrupt flag */

// LCDCCTL1
#define LCDFRMIE_H (0x0001u) /* LCD_C LCD frame interrupt enable */
#define LCDBLKOFFIE_H (0x0002u) /* LCD_C LCD blinking off interrupt flag, */
#define LCDBLKONIE_H (0x0004u) /* LCD_C LCD blinking on interrupt flag, */
#define LCDNOCAPIE_H (0x0008u) /* LCD_C No cpacitance connected interrupt enable */

// LCDCBLKCTL
#define LCDBLKMOD0 (0x0001u) /* LCD_C Blinking mode Bit: 0 */
#define LCDBLKMOD1 (0x0002u) /* LCD_C Blinking mode Bit: 1 */
#define LCDBLKPRE0 (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
#define LCDBLKPRE1 (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
#define LCDBLKPRE2 (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
#define LCDBLKDIV0 (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */
#define LCDBLKDIV1 (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */
#define LCDBLKDIV2 (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */

// LCDCBLKCTL
#define LCDBLKMOD0_L (0x0001u) /* LCD_C Blinking mode Bit: 0 */
#define LCDBLKMOD1_L (0x0002u) /* LCD_C Blinking mode Bit: 1 */
#define LCDBLKPRE0_L (0x0004u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
#define LCDBLKPRE1_L (0x0008u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
#define LCDBLKPRE2_L (0x0010u) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
#define LCDBLKDIV0_L (0x0020u) /* LCD_C Clock divider for blinking frequency Bit: 0 */
#define LCDBLKDIV1_L (0x0040u) /* LCD_C Clock divider for blinking frequency Bit: 1 */
#define LCDBLKDIV2_L (0x0080u) /* LCD_C Clock divider for blinking frequency Bit: 2 */

// LCDCBLKCTL

#define LCDBLKMOD_0 (0x0000u) /* LCD_C Blinking mode: Off */
#define LCDBLKMOD_1 (0x0001u) /* LCD_C Blinking mode: Individual */
#define LCDBLKMOD_2 (0x0002u) /* LCD_C Blinking mode: All */
#define LCDBLKMOD_3 (0x0003u) /* LCD_C Blinking mode: Switching */

// LCDCMEMCTL
#define LCDDISP (0x0001u) /* LCD_C LCD memory registers for display */
#define LCDCLRM (0x0002u) /* LCD_C Clear LCD memory */
#define LCDCLRBM (0x0004u) /* LCD_C Clear LCD blinking memory */

// LCDCMEMCTL
#define LCDDISP_L (0x0001u) /* LCD_C LCD memory registers for display */
#define LCDCLRM_L (0x0002u) /* LCD_C Clear LCD memory */
#define LCDCLRBM_L (0x0004u) /* LCD_C Clear LCD blinking memory */

// LCDCMEMCTL

// LCDCVCTL
#define LCD2B (0x0001u) /* Selects 1/2 bias. */
#define VLCDREF0 (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */
#define VLCDREF1 (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */
#define LCDCPEN (0x0008u) /* LCD Voltage Charge Pump Enable. */
#define VLCDEXT (0x0010u) /* Select external source for VLCD. */
#define LCDEXTBIAS (0x0020u) /* V2 - V4 voltage select. */
#define R03EXT (0x0040u) /* Selects external connections for LCD mid voltages. */
#define LCDREXT (0x0080u) /* Selects external connection for lowest LCD voltage. */
#define VLCD0 (0x0200u) /* VLCD select: 0 */
#define VLCD1 (0x0400u) /* VLCD select: 1 */
#define VLCD2 (0x0800u) /* VLCD select: 2 */
#define VLCD3 (0x1000u) /* VLCD select: 3 */
#define VLCD4 (0x2000u) /* VLCD select: 4 */
#define VLCD5 (0x4000u) /* VLCD select: 5 */

// LCDCVCTL
#define LCD2B_L (0x0001u) /* Selects 1/2 bias. */
#define VLCDREF0_L (0x0002u) /* Selects reference voltage for regulated charge pump: 0 */
#define VLCDREF1_L (0x0004u) /* Selects reference voltage for regulated charge pump: 1 */
#define LCDCPEN_L (0x0008u) /* LCD Voltage Charge Pump Enable. */
#define VLCDEXT_L (0x0010u) /* Select external source for VLCD. */
#define LCDEXTBIAS_L (0x0020u) /* V2 - V4 voltage select. */
#define R03EXT_L (0x0040u) /* Selects external connections for LCD mid voltages. */
#define LCDREXT_L (0x0080u) /* Selects external connection for lowest LCD voltage. */

// LCDCVCTL
#define VLCD0_H (0x0002u) /* VLCD select: 0 */
#define VLCD1_H (0x0004u) /* VLCD select: 1 */
#define VLCD2_H (0x0008u) /* VLCD select: 2 */
#define VLCD3_H (0x0010u) /* VLCD select: 3 */
#define VLCD4_H (0x0020u) /* VLCD select: 4 */
#define VLCD5_H (0x0040u) /* VLCD select: 5 */

/* Reference voltage source select for the regulated charge pump */
#define VLCDREF_0 (0<<1) /* Internal */
#define VLCDREF_1 (1<<1) /* External */
#define VLCDREF_2 (2<<1) /* Reserved */
#define VLCDREF_3 (3<<1) /* Reserved */

/* Charge pump voltage selections */
#define VLCD_0 (0<<9) /* Charge pump disabled */
#define VLCD_1 (1<<9) /* VLCD = 2.60V */
#define VLCD_2 (2<<9) /* VLCD = 2.66V */
#define VLCD_3 (3<<9) /* VLCD = 2.72V */
#define VLCD_4 (4<<9) /* VLCD = 2.78V */
#define VLCD_5 (5<<9) /* VLCD = 2.84V */
#define VLCD_6 (6<<9) /* VLCD = 2.90V */
#define VLCD_7 (7<<9) /* VLCD = 2.96V */
#define VLCD_8 (8<<9) /* VLCD = 3.02V */
#define VLCD_9 (9<<9) /* VLCD = 3.08V */
#define VLCD_10 (10<<9) /* VLCD = 3.14V */
#define VLCD_11 (11<<9) /* VLCD = 3.20V */
#define VLCD_12 (12<<9) /* VLCD = 3.26V */
#define VLCD_13 (13<<9) /* VLCD = 3.32V */
#define VLCD_14 (14<<9) /* VLCD = 3.38V */
#define VLCD_15 (15<<9) /* VLCD = 3.44V */

#define VLCD_DISABLED (0<<9) /* Charge pump disabled */
#define VLCD_2_60 (1<<9) /* VLCD = 2.60V */
#define VLCD_2_66 (2<<9) /* VLCD = 2.66V */
#define VLCD_2_72 (3<<9) /* VLCD = 2.72V */
#define VLCD_2_78 (4<<9) /* VLCD = 2.78V */
#define VLCD_2_84 (5<<9) /* VLCD = 2.84V */
#define VLCD_2_90 (6<<9) /* VLCD = 2.90V */
#define VLCD_2_96 (7<<9) /* VLCD = 2.96V */
#define VLCD_3_02 (8<<9) /* VLCD = 3.02V */
#define VLCD_3_08 (9<<9) /* VLCD = 3.08V */
#define VLCD_3_14 (10<<9) /* VLCD = 3.14V */
#define VLCD_3_20 (11<<9) /* VLCD = 3.20V */
#define VLCD_3_26 (12<<9) /* VLCD = 3.26V */
#define VLCD_3_32 (12<<9) /* VLCD = 3.32V */
#define VLCD_3_38 (13<<9) /* VLCD = 3.38V */
#define VLCD_3_44 (15<<9) /* VLCD = 3.44V */

// LCDCPCTL0
#define LCDS0 (0x0001u) /* LCD Segment 0 enable. */
#define LCDS1 (0x0002u) /* LCD Segment 1 enable. */
#define LCDS2 (0x0004u) /* LCD Segment 2 enable. */
#define LCDS3 (0x0008u) /* LCD Segment 3 enable. */
#define LCDS4 (0x0010u) /* LCD Segment 4 enable. */
#define LCDS5 (0x0020u) /* LCD Segment 5 enable. */
#define LCDS6 (0x0040u) /* LCD Segment 6 enable. */
#define LCDS7 (0x0080u) /* LCD Segment 7 enable. */
#define LCDS8 (0x0100u) /* LCD Segment 8 enable. */
#define LCDS9 (0x0200u) /* LCD Segment 9 enable. */
#define LCDS10 (0x0400u) /* LCD Segment 10 enable. */
#define LCDS11 (0x0800u) /* LCD Segment 11 enable. */
#define LCDS12 (0x1000u) /* LCD Segment 12 enable. */
#define LCDS13 (0x2000u) /* LCD Segment 13 enable. */
#define LCDS14 (0x4000u) /* LCD Segment 14 enable. */
#define LCDS15 (0x8000u) /* LCD Segment 15 enable. */

// LCDCPCTL0
#define LCDS0_L (0x0001u) /* LCD Segment 0 enable. */
#define LCDS1_L (0x0002u) /* LCD Segment 1 enable. */
#define LCDS2_L (0x0004u) /* LCD Segment 2 enable. */
#define LCDS3_L (0x0008u) /* LCD Segment 3 enable. */
#define LCDS4_L (0x0010u) /* LCD Segment 4 enable. */
#define LCDS5_L (0x0020u) /* LCD Segment 5 enable. */
#define LCDS6_L (0x0040u) /* LCD Segment 6 enable. */
#define LCDS7_L (0x0080u) /* LCD Segment 7 enable. */

// LCDCPCTL0
#define LCDS8_H (0x0001u) /* LCD Segment 8 enable. */
#define LCDS9_H (0x0002u) /* LCD Segment 9 enable. */
#define LCDS10_H (0x0004u) /* LCD Segment 10 enable. */
#define LCDS11_H (0x0008u) /* LCD Segment 11 enable. */
#define LCDS12_H (0x0010u) /* LCD Segment 12 enable. */
#define LCDS13_H (0x0020u) /* LCD Segment 13 enable. */
#define LCDS14_H (0x0040u) /* LCD Segment 14 enable. */
#define LCDS15_H (0x0080u) /* LCD Segment 15 enable. */

// LCDCPCTL1
#define LCDS16 (0x0001u) /* LCD Segment 16 enable. */
#define LCDS17 (0x0002u) /* LCD Segment 17 enable. */
#define LCDS18 (0x0004u) /* LCD Segment 18 enable. */
#define LCDS19 (0x0008u) /* LCD Segment 19 enable. */
#define LCDS20 (0x0010u) /* LCD Segment 20 enable. */
#define LCDS21 (0x0020u) /* LCD Segment 21 enable. */
#define LCDS22 (0x0040u) /* LCD Segment 22 enable. */
#define LCDS23 (0x0080u) /* LCD Segment 23 enable. */
#define LCDS24 (0x0100u) /* LCD Segment 24 enable. */
#define LCDS25 (0x0200u) /* LCD Segment 25 enable. */
#define LCDS26 (0x0400u) /* LCD Segment 26 enable. */
#define LCDS27 (0x0800u) /* LCD Segment 27 enable. */
#define LCDS28 (0x1000u) /* LCD Segment 28 enable. */
#define LCDS29 (0x2000u) /* LCD Segment 29 enable. */
#define LCDS30 (0x4000u) /* LCD Segment 30 enable. */
#define LCDS31 (0x8000u) /* LCD Segment 31 enable. */

// LCDCPCTL1
#define LCDS16_L (0x0001u) /* LCD Segment 16 enable. */
#define LCDS17_L (0x0002u) /* LCD Segment 17 enable. */
#define LCDS18_L (0x0004u) /* LCD Segment 18 enable. */
#define LCDS19_L (0x0008u) /* LCD Segment 19 enable. */
#define LCDS20_L (0x0010u) /* LCD Segment 20 enable. */
#define LCDS21_L (0x0020u) /* LCD Segment 21 enable. */
#define LCDS22_L (0x0040u) /* LCD Segment 22 enable. */
#define LCDS23_L (0x0080u) /* LCD Segment 23 enable. */

// LCDCPCTL1
#define LCDS24_H (0x0001u) /* LCD Segment 24 enable. */
#define LCDS25_H (0x0002u) /* LCD Segment 25 enable. */
#define LCDS26_H (0x0004u) /* LCD Segment 26 enable. */
#define LCDS27_H (0x0008u) /* LCD Segment 27 enable. */
#define LCDS28_H (0x0010u) /* LCD Segment 28 enable. */
#define LCDS29_H (0x0020u) /* LCD Segment 29 enable. */
#define LCDS30_H (0x0040u) /* LCD Segment 30 enable. */
#define LCDS31_H (0x0080u) /* LCD Segment 31 enable. */

// LCDCPCTL2
#define LCDS32 (0x0001u) /* LCD Segment 32 enable. */
#define LCDS33 (0x0002u) /* LCD Segment 33 enable. */
#define LCDS34 (0x0004u) /* LCD Segment 34 enable. */
#define LCDS35 (0x0008u) /* LCD Segment 35 enable. */
#define LCDS36 (0x0010u) /* LCD Segment 36 enable. */
#define LCDS37 (0x0020u) /* LCD Segment 37 enable. */
#define LCDS38 (0x0040u) /* LCD Segment 38 enable. */
#define LCDS39 (0x0080u) /* LCD Segment 39 enable. */
#define LCDS40 (0x0100u) /* LCD Segment 40 enable. */
#define LCDS41 (0x0200u) /* LCD Segment 41 enable. */
#define LCDS42 (0x0400u) /* LCD Segment 42 enable. */
#define LCDS43 (0x0800u) /* LCD Segment 43 enable. */
#define LCDS44 (0x1000u) /* LCD Segment 44 enable. */
#define LCDS45 (0x2000u) /* LCD Segment 45 enable. */
#define LCDS46 (0x4000u) /* LCD Segment 46 enable. */
#define LCDS47 (0x8000u) /* LCD Segment 47 enable. */

// LCDCPCTL2
#define LCDS32_L (0x0001u) /* LCD Segment 32 enable. */
#define LCDS33_L (0x0002u) /* LCD Segment 33 enable. */
#define LCDS34_L (0x0004u) /* LCD Segment 34 enable. */
#define LCDS35_L (0x0008u) /* LCD Segment 35 enable. */
#define LCDS36_L (0x0010u) /* LCD Segment 36 enable. */
#define LCDS37_L (0x0020u) /* LCD Segment 37 enable. */
#define LCDS38_L (0x0040u) /* LCD Segment 38 enable. */
#define LCDS39_L (0x0080u) /* LCD Segment 39 enable. */

// LCDCPCTL2
#define LCDS40_H (0x0001u) /* LCD Segment 40 enable. */
#define LCDS41_H (0x0002u) /* LCD Segment 41 enable. */
#define LCDS42_H (0x0004u) /* LCD Segment 42 enable. */
#define LCDS43_H (0x0008u) /* LCD Segment 43 enable. */
#define LCDS44_H (0x0010u) /* LCD Segment 44 enable. */
#define LCDS45_H (0x0020u) /* LCD Segment 45 enable. */
#define LCDS46_H (0x0040u) /* LCD Segment 46 enable. */
#define LCDS47_H (0x0080u) /* LCD Segment 47 enable. */

// LCDCCPCTL
#define LCDCPDIS0 (0x0001u) /* LCD charge pump disable */
#define LCDCPDIS1 (0x0002u) /* LCD charge pump disable */
#define LCDCPDIS2 (0x0004u) /* LCD charge pump disable */
#define LCDCPDIS3 (0x0008u) /* LCD charge pump disable */
#define LCDCPDIS4 (0x0010u) /* LCD charge pump disable */
#define LCDCPDIS5 (0x0020u) /* LCD charge pump disable */
#define LCDCPDIS6 (0x0040u) /* LCD charge pump disable */
#define LCDCPDIS7 (0x0080u) /* LCD charge pump disable */
#define LCDCPCLKSYNC (0x8000u) /* LCD charge pump clock synchronization */

// LCDCCPCTL
#define LCDCPDIS0_L (0x0001u) /* LCD charge pump disable */
#define LCDCPDIS1_L (0x0002u) /* LCD charge pump disable */
#define LCDCPDIS2_L (0x0004u) /* LCD charge pump disable */
#define LCDCPDIS3_L (0x0008u) /* LCD charge pump disable */
#define LCDCPDIS4_L (0x0010u) /* LCD charge pump disable */
#define LCDCPDIS5_L (0x0020u) /* LCD charge pump disable */
#define LCDCPDIS6_L (0x0040u) /* LCD charge pump disable */
#define LCDCPDIS7_L (0x0080u) /* LCD charge pump disable */

// LCDCCPCTL
#define LCDCPCLKSYNC_H (0x0080u) /* LCD charge pump clock synchronization */

#define LCDM1_ (0x0A20u) /* LCD Memory 1 */
DEFC( LCDM1 , LCDM1_)
#define LCDMEM_ LCDM1 /* LCD Memory */
#ifndef __IAR_SYSTEMS_ICC__
#define LCDMEM LCDM1 /* LCD Memory (for assembler) */
#else
#define LCDMEM ((char*) &LCDM1) /* LCD Memory (for C) */
#endif
#define LCDM2_ (0x0A21u) /* LCD Memory 2 */
DEFC( LCDM2 , LCDM2_)
#define LCDM3_ (0x0A22u) /* LCD Memory 3 */
DEFC( LCDM3 , LCDM3_)
#define LCDM4_ (0x0A23u) /* LCD Memory 4 */
DEFC( LCDM4 , LCDM4_)
#define LCDM5_ (0x0A24u) /* LCD Memory 5 */
DEFC( LCDM5 , LCDM5_)
#define LCDM6_ (0x0A25u) /* LCD Memory 6 */
DEFC( LCDM6 , LCDM6_)
#define LCDM7_ (0x0A26u) /* LCD Memory 7 */
DEFC( LCDM7 , LCDM7_)
#define LCDM8_ (0x0A27u) /* LCD Memory 8 */
DEFC( LCDM8 , LCDM8_)
#define LCDM9_ (0x0A28u) /* LCD Memory 9 */
DEFC( LCDM9 , LCDM9_)
#define LCDM10_ (0x0A29u) /* LCD Memory 10 */
DEFC( LCDM10 , LCDM10_)
#define LCDM11_ (0x0A2Au) /* LCD Memory 11 */
DEFC( LCDM11 , LCDM11_)
#define LCDM12_ (0x0A2Bu) /* LCD Memory 12 */
DEFC( LCDM12 , LCDM12_)
#define LCDM13_ (0x0A2Cu) /* LCD Memory 13 */
DEFC( LCDM13 , LCDM13_)
#define LCDM14_ (0x0A2Du) /* LCD Memory 14 */
DEFC( LCDM14 , LCDM14_)
#define LCDM15_ (0x0A2Eu) /* LCD Memory 15 */
DEFC( LCDM15 , LCDM15_)
#define LCDM16_ (0x0A2Fu) /* LCD Memory 16 */
DEFC( LCDM16 , LCDM16_)
#define LCDM17_ (0x0A30u) /* LCD Memory 17 */
DEFC( LCDM17 , LCDM17_)
#define LCDM18_ (0x0A31u) /* LCD Memory 18 */
DEFC( LCDM18 , LCDM18_)
#define LCDM19_ (0x0A32u) /* LCD Memory 19 */
DEFC( LCDM19 , LCDM19_)
#define LCDM20_ (0x0A33u) /* LCD Memory 20 */
DEFC( LCDM20 , LCDM20_)
#define LCDM21_ (0x0A34u) /* LCD Memory 21 */
DEFC( LCDM21 , LCDM21_)
#define LCDM22_ (0x0A35u) /* LCD Memory 22 */
DEFC( LCDM22 , LCDM22_)
#define LCDM23_ (0x0A36u) /* LCD Memory 23 */
DEFC( LCDM23 , LCDM23_)
#define LCDM24_ (0x0A37u) /* LCD Memory 24 */
DEFC( LCDM24 , LCDM24_)
#define LCDM25_ (0x0A38u) /* LCD Memory 25 */
DEFC( LCDM25 , LCDM25_)
#define LCDM26_ (0x0A39u) /* LCD Memory 26 */
DEFC( LCDM26 , LCDM26_)
#define LCDM27_ (0x0A3Au) /* LCD Memory 27 */
DEFC( LCDM27 , LCDM27_)
#define LCDM28_ (0x0A3Bu) /* LCD Memory 28 */
DEFC( LCDM28 , LCDM28_)
#define LCDM29_ (0x0A3Cu) /* LCD Memory 29 */
DEFC( LCDM29 , LCDM29_)
#define LCDM30_ (0x0A3Du) /* LCD Memory 30 */
DEFC( LCDM30 , LCDM30_)
#define LCDM31_ (0x0A3Eu) /* LCD Memory 31 */
DEFC( LCDM31 , LCDM31_)
#define LCDM32_ (0x0A3Fu) /* LCD Memory 32 */
DEFC( LCDM32 , LCDM32_)
#define LCDM33_ (0x0A40u) /* LCD Memory 33 */
DEFC( LCDM33 , LCDM33_)
#define LCDM34_ (0x0A41u) /* LCD Memory 34 */
DEFC( LCDM34 , LCDM34_)
#define LCDM35_ (0x0A42u) /* LCD Memory 35 */
DEFC( LCDM35 , LCDM35_)
#define LCDM36_ (0x0A43u) /* LCD Memory 36 */
DEFC( LCDM36 , LCDM36_)
#define LCDM37_ (0x0A44u) /* LCD Memory 37 */
DEFC( LCDM37 , LCDM37_)
#define LCDM38_ (0x0A45u) /* LCD Memory 38 */
DEFC( LCDM38 , LCDM38_)
#define LCDM39_ (0x0A46u) /* LCD Memory 39 */
DEFC( LCDM39 , LCDM39_)
#define LCDM40_ (0x0A47u) /* LCD Memory 40 */
DEFC( LCDM40 , LCDM40_)

#define LCDBM1 LCDM33 /* LCD Blinking Memory 1 */
#define LCDBM1_ LCDM33 /* LCD Blinking Memory 1 */
#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
#ifndef __IAR_SYSTEMS_ICC__
#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
#else
#define LCDBMEM ((char*) &LCDBM1) /* LCD Blinking Memory (for C) */
#endif
#define LCDBM2 LCDM34 /* LCD Blinking Memory 2 */
#define LCDBM2_ LCDM34 /* LCD Blinking Memory 2 */
#define LCDBM3 LCDM35 /* LCD Blinking Memory 3 */
#define LCDBM3_ LCDM35 /* LCD Blinking Memory 3 */
#define LCDBM4 LCDM36 /* LCD Blinking Memory 4 */
#define LCDBM4_ LCDM36 /* LCD Blinking Memory 4 */
#define LCDBM5 LCDM37 /* LCD Blinking Memory 5 */
#define LCDBM5_ LCDM37 /* LCD Blinking Memory 5 */
#define LCDBM6 LCDM38 /* LCD Blinking Memory 6 */
#define LCDBM6_ LCDM38 /* LCD Blinking Memory 6 */
#define LCDBM7 LCDM39 /* LCD Blinking Memory 7 */
#define LCDBM7_ LCDM39 /* LCD Blinking Memory 7 */
#define LCDBM8 LCDM40 /* LCD Blinking Memory 8 */
#define LCDBM8_ LCDM40 /* LCD Blinking Memory 8 */
#define LCDBM9_ (0x0A48u) /* LCD Blinking Memory 9 */
DEFC( LCDBM9 , LCDBM9_)
#define LCDBM10_ (0x0A49u) /* LCD Blinking Memory 10 */
DEFC( LCDBM10 , LCDBM10_)
#define LCDBM11_ (0x0A4Au) /* LCD Blinking Memory 11 */
DEFC( LCDBM11 , LCDBM11_)
#define LCDBM12_ (0x0A4Bu) /* LCD Blinking Memory 12 */
DEFC( LCDBM12 , LCDBM12_)
#define LCDBM13_ (0x0A4Cu) /* LCD Blinking Memory 13 */
DEFC( LCDBM13 , LCDBM13_)
#define LCDBM14_ (0x0A4Du) /* LCD Blinking Memory 14 */
DEFC( LCDBM14 , LCDBM14_)
#define LCDBM15_ (0x0A4Eu) /* LCD Blinking Memory 15 */
DEFC( LCDBM15 , LCDBM15_)
#define LCDBM16_ (0x0A4Fu) /* LCD Blinking Memory 16 */
DEFC( LCDBM16 , LCDBM16_)
#define LCDBM17_ (0x0A50u) /* LCD Blinking Memory 17 */
DEFC( LCDBM17 , LCDBM17_)
#define LCDBM18_ (0x0A51u) /* LCD Blinking Memory 18 */
DEFC( LCDBM18 , LCDBM18_)
#define LCDBM19_ (0x0A52u) /* LCD Blinking Memory 19 */
DEFC( LCDBM19 , LCDBM19_)
#define LCDBM20_ (0x0A53u) /* LCD Blinking Memory 20 */
DEFC( LCDBM20 , LCDBM20_)

/* LCDCIV Definitions */
#define LCDCIV_NONE (0x0000u) /* No Interrupt pending */
#define LCDCIV_LCDNOCAPIFG (0x0002u) /* No capacitor connected */
#define LCDCIV_LCDCLKOFFIFG (0x0004u) /* Blink, segments off */
#define LCDCIV_LCDCLKONIFG (0x0006u) /* Blink, segments on */
#define LCDCIV_LCDFRMIFG (0x0008u) /* Frame interrupt */

/************************************************************
* HARDWARE MULTIPLIER 32Bit
************************************************************/
#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_MPY32__ 0x04C0

#define MPY_ (0x04C0u) /* Multiply Unsigned/Operand 1 */
DEFCW( MPY , MPY_)
#define MPYS_ (0x04C2u) /* Multiply Signed/Operand 1 */
DEFCW( MPYS , MPYS_)
#define MAC_ (0x04C4u) /* Multiply Unsigned and Accumulate/Operand 1 */
DEFCW( MAC , MAC_)
#define MACS_ (0x04C6u) /* Multiply Signed and Accumulate/Operand 1 */
DEFCW( MACS , MACS_)
#define OP2_ (0x04C8u) /* Operand 2 */
DEFCW( OP2 , OP2_)
#define RESLO_ (0x04CAu) /* Result Low Word */
DEFCW( RESLO , RESLO_)
#define RESHI_ (0x04CCu) /* Result High Word */
DEFCW( RESHI , RESHI_)
#define SUMEXT_ (0x04CEu) /* Sum Extend */
READ_ONLY_DEFCW( SUMEXT , SUMEXT_)

#define MPY32L_ (0x04D0u) /* 32-bit operand 1 - multiply - low word */
DEFCW( MPY32L , MPY32L_)
#define MPY32H_ (0x04D2u) /* 32-bit operand 1 - multiply - high word */
DEFCW( MPY32H , MPY32H_)
#define MPYS32L_ (0x04D4u) /* 32-bit operand 1 - signed multiply - low word */
DEFCW( MPYS32L , MPYS32L_)
#define MPYS32H_ (0x04D6u) /* 32-bit operand 1 - signed multiply - high word */
DEFCW( MPYS32H , MPYS32H_)
#define MAC32L_ (0x04D8u) /* 32-bit operand 1 - multiply accumulate - low word */
DEFCW( MAC32L , MAC32L_)
#define MAC32H_ (0x04DAu) /* 32-bit operand 1 - multiply accumulate - high word */
DEFCW( MAC32H , MAC32H_)
#define MACS32L_ (0x04DCu) /* 32-bit operand 1 - signed multiply accumulate - low word */
DEFCW( MACS32L , MACS32L_)
#define MACS32H_ (0x04DEu) /* 32-bit operand 1 - signed multiply accumulate - high word */
DEFCW( MACS32H , MACS32H_)
#define OP2L_ (0x04E0u) /* 32-bit operand 2 - low word */
DEFCW( OP2L , OP2L_)
#define OP2H_ (0x04E2u) /* 32-bit operand 2 - high word */
DEFCW( OP2H , OP2H_)
#define RES0_ (0x04E4u) /* 32x32-bit result 0 - least significant word */
DEFCW( RES0 , RES0_)
#define RES1_ (0x04E6u) /* 32x32-bit result 1 */
DEFCW( RES1 , RES1_)
#define RES2_ (0x04E8u) /* 32x32-bit result 2 */
DEFCW( RES2 , RES2_)
#define RES3_ (0x04EAu) /* 32x32-bit result 3 - most significant word */
DEFCW( RES3 , RES3_)
#define MPY32CTL0_ (0x04ECu) /* MPY32 Control Register 0 */
DEFCW( MPY32CTL0 , MPY32CTL0_)

#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
#define OP2_B OP2_L /* Operand 2 (Byte Access) */
#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */

/* MPY32CTL0 Control Bits */
#define MPYC (0x0001u) /* Carry of the multiplier */
//#define RESERVED (0x0002u) /* Reserved */
#define MPYFRAC (0x0004u) /* Fractional mode */
#define MPYSAT (0x0008u) /* Saturation mode */
#define MPYM0 (0x0010u) /* Multiplier mode Bit:0 */
#define MPYM1 (0x0020u) /* Multiplier mode Bit:1 */
#define OP1_32 (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
#define OP2_32 (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
#define MPYDLYWRTEN (0x0100u) /* Delayed write enable */
#define MPYDLY32 (0x0200u) /* Delayed write mode */

/* MPY32CTL0 Control Bits */
#define MPYC_L (0x0001u) /* Carry of the multiplier */
//#define RESERVED (0x0002u) /* Reserved */
#define MPYFRAC_L (0x0004u) /* Fractional mode */
#define MPYSAT_L (0x0008u) /* Saturation mode */
#define MPYM0_L (0x0010u) /* Multiplier mode Bit:0 */
#define MPYM1_L (0x0020u) /* Multiplier mode Bit:1 */
#define OP1_32_L (0x0040u) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
#define OP2_32_L (0x0080u) /* Bit-width of operand 2 0:16Bit / 1:32Bit */

/* MPY32CTL0 Control Bits */
//#define RESERVED (0x0002u) /* Reserved */
#define MPYDLYWRTEN_H (0x0001u) /* Delayed write enable */
#define MPYDLY32_H (0x0002u) /* Delayed write mode */

#define MPYM_0 (0x0000u) /* Multiplier mode: MPY */
#define MPYM_1 (0x0010u) /* Multiplier mode: MPYS */
#define MPYM_2 (0x0020u) /* Multiplier mode: MAC */
#define MPYM_3 (0x0030u) /* Multiplier mode: MACS */
#define MPYM__MPY (0x0000u) /* Multiplier mode: MPY */
#define MPYM__MPYS (0x0010u) /* Multiplier mode: MPYS */
#define MPYM__MAC (0x0020u) /* Multiplier mode: MAC */
#define MPYM__MACS (0x0030u) /* Multiplier mode: MACS */

/************************************************************
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200

#define PAIN_ (0x0200u) /* Port A Input */
READ_ONLY_DEFCW( PAIN , PAIN_)
//#define PAOUT_ (0x0202u) /* Port A Output */
//DEFCW( PAOUT , PAOUT_)
//#define PADIR_ (0x0204u) /* Port A Direction */
//DEFCW( PADIR , PADIR_)
#define PAREN_ (0x0206u) /* Port A Resistor Enable */
DEFCW( PAREN , PAREN_)
#define PADS_ (0x0208u) /* Port A Drive Strenght */
DEFCW( PADS , PADS_)
#define PASEL_ (0x020Au) /* Port A Selection */
DEFCW( PASEL , PASEL_)
#define PAIES_ (0x0218u) /* Port A Interrupt Edge Select */
DEFCW( PAIES , PAIES_)
#define PAIE_ (0x021Au) /* Port A Interrupt Enable */
DEFCW( PAIE , PAIE_)
#define PAIFG_ (0x021Cu) /* Port A Interrupt Flag */
DEFCW( PAIFG , PAIFG_)


#define P1IV_ (0x020Eu) /* Port 1 Interrupt Vector Word */
DEFW( P1IV , P1IV_)
#define P2IV_ (0x021Eu) /* Port 2 Interrupt Vector Word */
DEFW( P2IV , P2IV_)
#define P1IN (PAIN_L) /* Port 1 Input */
//#define P1OUT (PAOUT_L) /* Port 1 Output */
//#define P1DIR (PADIR_L) /* Port 1 Direction */
#define P1REN (PAREN_L) /* Port 1 Resistor Enable */
#define P1DS (PADS_L) /* Port 1 Drive Strenght */
#define P1SEL (PASEL_L) /* Port 1 Selection */
#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */

//Definitions for P1IV
#define P1IV_NONE (0x0000u) /* No Interrupt pending */
#define P1IV_P1IFG0 (0x0002u) /* P1IV P1IFG.0 */
#define P1IV_P1IFG1 (0x0004u) /* P1IV P1IFG.1 */
#define P1IV_P1IFG2 (0x0006u) /* P1IV P1IFG.2 */
#define P1IV_P1IFG3 (0x0008u) /* P1IV P1IFG.3 */
#define P1IV_P1IFG4 (0x000Au) /* P1IV P1IFG.4 */
#define P1IV_P1IFG5 (0x000Cu) /* P1IV P1IFG.5 */
#define P1IV_P1IFG6 (0x000Eu) /* P1IV P1IFG.6 */
#define P1IV_P1IFG7 (0x0010u) /* P1IV P1IFG.7 */

#define P2IN (PAIN_H) /* Port 2 Input */
//#define P2OUT (PAOUT_H) /* Port 2 Output */
//#define P2DIR (PADIR_H) /* Port 2 Direction */
#define P2REN (PAREN_H) /* Port 2 Resistor Enable */
#define P2DS (PADS_H) /* Port 2 Drive Strenght */
#define P2SEL (PASEL_H) /* Port 2 Selection */
#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */

//Definitions for P2IV
#define P2IV_NONE (0x0000u) /* No Interrupt pending */
#define P2IV_P2IFG0 (0x0002u) /* P2IV P2IFG.0 */
#define P2IV_P2IFG1 (0x0004u) /* P2IV P2IFG.1 */
#define P2IV_P2IFG2 (0x0006u) /* P2IV P2IFG.2 */
#define P2IV_P2IFG3 (0x0008u) /* P2IV P2IFG.3 */
#define P2IV_P2IFG4 (0x000Au) /* P2IV P2IFG.4 */
#define P2IV_P2IFG5 (0x000Cu) /* P2IV P2IFG.5 */
#define P2IV_P2IFG6 (0x000Eu) /* P2IV P2IFG.6 */
#define P2IV_P2IFG7 (0x0010u) /* P2IV P2IFG.7 */


/************************************************************
* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220

#define PBIN_ (0x0220u) /* Port B Input */
READ_ONLY_DEFCW( PBIN , PBIN_)
//#define PBOUT_ (0x0222u) /* Port B Output */
//DEFCW( PBOUT , PBOUT_)
//#define PBDIR_ (0x0224u) /* Port B Direction */
//DEFCW( PBDIR , PBDIR_)
#define PBREN_ (0x0226u) /* Port B Resistor Enable */
DEFCW( PBREN , PBREN_)
#define PBDS_ (0x0228u) /* Port B Drive Strenght */
DEFCW( PBDS , PBDS_)
#define PBSEL_ (0x022Au) /* Port B Selection */
DEFCW( PBSEL , PBSEL_)


#define P3IN (PBIN_L) /* Port 3 Input */
//#define P3OUT (PBOUT_L) /* Port 3 Output */
//#define P3DIR (PBDIR_L) /* Port 3 Direction */
#define P3REN (PBREN_L) /* Port 3 Resistor Enable */
#define P3DS (PBDS_L) /* Port 3 Drive Strenght */
#define P3SEL (PBSEL_L) /* Port 3 Selection */

#define P4IN (PBIN_H) /* Port 4 Input */
//#define P4OUT (PBOUT_H) /* Port 4 Output */
//#define P4DIR (PBDIR_H) /* Port 4 Direction */
#define P4REN (PBREN_H) /* Port 4 Resistor Enable */
#define P4DS (PBDS_H) /* Port 4 Drive Strenght */
#define P4SEL (PBSEL_H) /* Port 4 Selection */


/************************************************************
* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240
#define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240
#define __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240

#define PCIN_ (0x0240u) /* Port C Input */
READ_ONLY_DEFCW( PCIN , PCIN_)
#define PCOUT_ (0x0242u) /* Port C Output */
DEFCW( PCOUT , PCOUT_)
#define PCDIR_ (0x0244u) /* Port C Direction */
DEFCW( PCDIR , PCDIR_)
#define PCREN_ (0x0246u) /* Port C Resistor Enable */
DEFCW( PCREN , PCREN_)
#define PCDS_ (0x0248u) /* Port C Drive Strenght */
DEFCW( PCDS , PCDS_)
#define PCSEL_ (0x024Au) /* Port C Selection */
DEFCW( PCSEL , PCSEL_)


#define P5IN (PCIN_L) /* Port 5 Input */
#define P5OUT (PCOUT_L) /* Port 5 Output */
#define P5DIR (PCDIR_L) /* Port 5 Direction */
#define P5REN (PCREN_L) /* Port 5 Resistor Enable */
#define P5DS (PCDS_L) /* Port 5 Drive Strenght */
#define P5SEL (PCSEL_L) /* Port 5 Selection */

#define P6IN (PCIN_H) /* Port 6 Input */
#define P6OUT (PCOUT_H) /* Port 6 Output */
#define P6DIR (PCDIR_H) /* Port 6 Direction */
#define P6REN (PCREN_H) /* Port 6 Resistor Enable */
#define P6DS (PCDS_H) /* Port 6 Drive Strenght */
#define P6SEL (PCSEL_H) /* Port 6 Selection */


/************************************************************
* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260
#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260
#define __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260

#define PDIN_ (0x0260u) /* Port D Input */
READ_ONLY_DEFCW( PDIN , PDIN_)
#define PDOUT_ (0x0262u) /* Port D Output */
DEFCW( PDOUT , PDOUT_)
#define PDDIR_ (0x0264u) /* Port D Direction */
DEFCW( PDDIR , PDDIR_)
#define PDREN_ (0x0266u) /* Port D Resistor Enable */
DEFCW( PDREN , PDREN_)
#define PDDS_ (0x0268u) /* Port D Drive Strenght */
DEFCW( PDDS , PDDS_)
#define PDSEL_ (0x026Au) /* Port D Selection */
DEFCW( PDSEL , PDSEL_)


#define P7IN (PDIN_L) /* Port 7 Input */
#define P7OUT (PDOUT_L) /* Port 7 Output */
#define P7DIR (PDDIR_L) /* Port 7 Direction */
#define P7REN (PDREN_L) /* Port 7 Resistor Enable */
#define P7DS (PDDS_L) /* Port 7 Drive Strenght */
#define P7SEL (PDSEL_L) /* Port 7 Selection */

#define P8IN (PDIN_H) /* Port 8 Input */
#define P8OUT (PDOUT_H) /* Port 8 Output */
#define P8DIR (PDDIR_H) /* Port 8 Direction */
#define P8REN (PDREN_H) /* Port 8 Resistor Enable */
#define P8DS (PDDS_H) /* Port 8 Drive Strenght */
#define P8SEL (PDSEL_H) /* Port 8 Selection */


/************************************************************
* DIGITAL I/O Port9 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT9_R__ 0x0280
#define __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORTE_R__ 0x0280

#define PEIN_ (0x0280u) /* Port E Input */
READ_ONLY_DEFCW( PEIN , PEIN_)
#define PEOUT_ (0x0282u) /* Port E Output */
DEFCW( PEOUT , PEOUT_)
#define PEDIR_ (0x0284u) /* Port E Direction */
DEFCW( PEDIR , PEDIR_)
#define PEREN_ (0x0286u) /* Port E Resistor Enable */
DEFCW( PEREN , PEREN_)
#define PEDS_ (0x0288u) /* Port E Drive Strenght */
DEFCW( PEDS , PEDS_)
#define PESEL_ (0x028Au) /* Port E Selection */
DEFCW( PESEL , PESEL_)


#define P9IN (PEIN_L) /* Port 9 Input */
#define P9OUT (PEOUT_L) /* Port 9 Output */
#define P9DIR (PEDIR_L) /* Port 9 Direction */
#define P9REN (PEREN_L) /* Port 9 Resistor Enable */
#define P9DS (PEDS_L) /* Port 9 Drive Strenght */
#define P9SEL (PESEL_L) /* Port 9 Selection */


/************************************************************
* DIGITAL I/O PortJ Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320

#define PJIN_ (0x0320u) /* Port J Input */
READ_ONLY_DEFCW( PJIN , PJIN_)
#define PJOUT_ (0x0322u) /* Port J Output */
DEFCW( PJOUT , PJOUT_)
#define PJDIR_ (0x0324u) /* Port J Direction */
DEFCW( PJDIR , PJDIR_)
#define PJREN_ (0x0326u) /* Port J Resistor Enable */
DEFCW( PJREN , PJREN_)
#define PJDS_ (0x0328u) /* Port J Drive Strenght */
DEFCW( PJDS , PJDS_)
#define PJSEL_ (0x032Au) /* Port J Selection */
DEFCW( PJSEL , PJSEL_)

/************************************************************
* PORT MAPPING CONTROLLER
************************************************************/
#define __MSP430_HAS_PORT_MAPPING__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT_MAPPING__ 0x01C0

#define PMAPKEYID_ (0x01C0u) /* Port Mapping Key register */
DEFCW( PMAPKEYID , PMAPKEYID_)
#define PMAPCTL_ (0x01C2u) /* Port Mapping control register */
DEFCW( PMAPCTL , PMAPCTL_)

#define PMAPKEY (0x2D52u) /* Port Mapping Key */
#define PMAPPWD PMAPKEYID /* Legacy Definition: Mapping Key register */
#define PMAPPW (0x2D52u) /* Legacy Definition: Port Mapping Password */

/* PMAPCTL Control Bits */
#define PMAPLOCKED (0x0001u) /* Port Mapping Lock bit. Read only */
#define PMAPRECFG (0x0002u) /* Port Mapping re-configuration control bit */

/* PMAPCTL Control Bits */
#define PMAPLOCKED_L (0x0001u) /* Port Mapping Lock bit. Read only */
#define PMAPRECFG_L (0x0002u) /* Port Mapping re-configuration control bit */

/* PMAPCTL Control Bits */

/************************************************************
* PORT 1 MAPPING CONTROLLER
************************************************************/
#define __MSP430_HAS_PORT1_MAPPING__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT1_MAPPING__ 0x01C8

#define P1MAP01_ (0x01C8u) /* Port P1.0/1 mapping register */
DEFCW( P1MAP01 , P1MAP01_)
#define P1MAP23_ (0x01CAu) /* Port P1.2/3 mapping register */
DEFCW( P1MAP23 , P1MAP23_)
#define P1MAP45_ (0x01CCu) /* Port P1.4/5 mapping register */
DEFCW( P1MAP45 , P1MAP45_)
#define P1MAP67_ (0x01CEu) /* Port P1.6/7 mapping register */
DEFCW( P1MAP67 , P1MAP67_)
#define P1MAP0 P1MAP01_L /* Port P1.0 mapping register */
#define P1MAP1 P1MAP01_H /* Port P1.1 mapping register */
#define P1MAP2 P1MAP23_L /* Port P1.2 mapping register */
#define P1MAP3 P1MAP23_H /* Port P1.3 mapping register */
#define P1MAP4 P1MAP45_L /* Port P1.4 mapping register */
#define P1MAP5 P1MAP45_H /* Port P1.5 mapping register */
#define P1MAP6 P1MAP67_L /* Port P1.6 mapping register */
#define P1MAP7 P1MAP67_H /* Port P1.7 mapping register */

/************************************************************
* PORT 2 MAPPING CONTROLLER
************************************************************/
#define __MSP430_HAS_PORT2_MAPPING__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT2_MAPPING__ 0x01D0

#define P2MAP01_ (0x01D0u) /* Port P2.0/1 mapping register */
DEFCW( P2MAP01 , P2MAP01_)
#define P2MAP23_ (0x01D2u) /* Port P2.2/3 mapping register */
DEFCW( P2MAP23 , P2MAP23_)
#define P2MAP45_ (0x01D4u) /* Port P2.4/5 mapping register */
DEFCW( P2MAP45 , P2MAP45_)
#define P2MAP67_ (0x01D6u) /* Port P2.6/7 mapping register */
DEFCW( P2MAP67 , P2MAP67_)
#define P2MAP0 P2MAP01_L /* Port P2.0 mapping register */
#define P2MAP1 P2MAP01_H /* Port P2.1 mapping register */
#define P2MAP2 P2MAP23_L /* Port P2.2 mapping register */
#define P2MAP3 P2MAP23_H /* Port P2.3 mapping register */
#define P2MAP4 P2MAP45_L /* Port P2.4 mapping register */
#define P2MAP5 P2MAP45_H /* Port P2.5 mapping register */
#define P2MAP6 P2MAP67_L /* Port P2.6 mapping register */
#define P2MAP7 P2MAP67_H /* Port P2.7 mapping register */

/************************************************************
* PORT 3 MAPPING CONTROLLER
************************************************************/
#define __MSP430_HAS_PORT3_MAPPING__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PORT3_MAPPING__ 0x01D8

#define P3MAP01_ (0x01D8u) /* Port P3.0/1 mapping register */
DEFCW( P3MAP01 , P3MAP01_)
#define P3MAP23_ (0x01DAu) /* Port P3.2/3 mapping register */
DEFCW( P3MAP23 , P3MAP23_)
#define P3MAP45_ (0x01DCu) /* Port P3.4/5 mapping register */
DEFCW( P3MAP45 , P3MAP45_)
#define P3MAP67_ (0x01DEu) /* Port P3.6/7 mapping register */
DEFCW( P3MAP67 , P3MAP67_)
#define P3MAP0 P3MAP01_L /* Port P3.0 mapping register */
#define P3MAP1 P3MAP01_H /* Port P3.1 mapping register */
#define P3MAP2 P3MAP23_L /* Port P3.2 mapping register */
#define P3MAP3 P3MAP23_H /* Port P3.3 mapping register */
#define P3MAP4 P3MAP45_L /* Port P3.4 mapping register */
#define P3MAP5 P3MAP45_H /* Port P3.5 mapping register */
#define P3MAP6 P3MAP67_L /* Port P3.6 mapping register */
#define P3MAP7 P3MAP67_H /* Port P3.7 mapping register */

#define PM_NONE 0
#define PM_UCA0RXD 1
#define PM_UCA0SOMI 1
#define PM_UCA0TXD 2
#define PM_UCA0SIMO 2
#define PM_UCA0CLK 3
#define PM_UCA0STE 4
#define PM_UCA1RXD 5
#define PM_UCA1SOMI 5
#define PM_UCA1TXD 6
#define PM_UCA1SIMO 6
#define PM_UCA1CLK 7
#define PM_UCA1STE 8
#define PM_UCA2RXD 9
#define PM_UCA2SOMI 9
#define PM_UCA2TXD 10
#define PM_UCA2SIMO 10
#define PM_UCA2CLK 11
#define PM_UCA2STE 12
#define PM_UCB0SIMO 13
#define PM_UCB0SDA 13
#define PM_UCB0SOMI 14
#define PM_UCB0SCL 14
#define PM_UCB0CLK 15
#define PM_UCB0STE 16
#define PM_TA0_0 17
#define PM_TA0_1 18
#define PM_TA0_2 19
#define PM_TA1_0 20
#define PM_TA1_1 21
#define PM_TA2_0 22
#define PM_TA2_1 23
#define PM_TA3_0 24
#define PM_TA3_1 25
#define PM_TACLK 26
#define PM_RTCCLK 26
#define PM_SDCLK 27
#define PM_SD0DIO 28
#define PM_SD1DIO 29
#define PM_SD2DIO 30
#define PM_ANALOG 31

/************************************************************
* PMM - Power Management System
************************************************************/
#define __MSP430_HAS_PMM__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_PMM__ 0x0120

#define PMMCTL0_ (0x0120u) /* PMM Control 0 */
DEFCW( PMMCTL0 , PMMCTL0_)
#define PMMCTL1_ (0x0122u) /* PMM Control 1 */
DEFCW( PMMCTL1 , PMMCTL1_)
#define SVSMHCTL_ (0x0124u) /* SVS and SVM high side control register */
DEFCW( SVSMHCTL , SVSMHCTL_)
#define SVSMLCTL_ (0x0126u) /* SVS and SVM low side control register */
DEFCW( SVSMLCTL , SVSMLCTL_)
#define SVSMIO_ (0x0128u) /* SVSIN and SVSOUT control register */
DEFCW( SVSMIO , SVSMIO_)
#define PMMIFG_ (0x012Cu) /* PMM Interrupt Flag */
DEFCW( PMMIFG , PMMIFG_)
#define PMMRIE_ (0x012Eu) /* PMM and RESET Interrupt Enable */
DEFCW( PMMRIE , PMMRIE_)
#define PM5CTL0_ (0x0130u) /* PMM Power Mode 5 Control Register 0 */
DEFCW( PM5CTL0 , PM5CTL0_)

#define PMMPW (0xA500u) /* PMM Register Write Password */
#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */

/* PMMCTL0 Control Bits */
#define PMMCOREV0 (0x0001u) /* PMM Core Voltage Bit: 0 */
#define PMMCOREV1 (0x0002u) /* PMM Core Voltage Bit: 1 */
#define PMMSWBOR (0x0004u) /* PMM Software BOR */
#define PMMSWPOR (0x0008u) /* PMM Software POR */
#define PMMREGOFF (0x0010u) /* PMM Turn Regulator off */
#define PMMHPMRE (0x0080u) /* PMM Global High Power Module Request Enable */

/* PMMCTL0 Control Bits */
#define PMMCOREV0_L (0x0001u) /* PMM Core Voltage Bit: 0 */
#define PMMCOREV1_L (0x0002u) /* PMM Core Voltage Bit: 1 */
#define PMMSWBOR_L (0x0004u) /* PMM Software BOR */
#define PMMSWPOR_L (0x0008u) /* PMM Software POR */
#define PMMREGOFF_L (0x0010u) /* PMM Turn Regulator off */
#define PMMHPMRE_L (0x0080u) /* PMM Global High Power Module Request Enable */

/* PMMCTL0 Control Bits */

#define PMMCOREV_0 (0x0000u) /* PMM Core Voltage 0 (1.35V) */
#define PMMCOREV_1 (0x0001u) /* PMM Core Voltage 1 (1.55V) */
#define PMMCOREV_2 (0x0002u) /* PMM Core Voltage 2 (1.75V) */
#define PMMCOREV_3 (0x0003u) /* PMM Core Voltage 3 (1.85V) */

/* PMMCTL1 Control Bits */
#define PMMREFMD (0x0001u) /* PMM Reference Mode */
#define PMMCMD0 (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */
#define PMMCMD1 (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */

/* PMMCTL1 Control Bits */
#define PMMREFMD_L (0x0001u) /* PMM Reference Mode */
#define PMMCMD0_L (0x0010u) /* PMM Voltage Regulator Current Mode Bit: 0 */
#define PMMCMD1_L (0x0020u) /* PMM Voltage Regulator Current Mode Bit: 1 */

/* PMMCTL1 Control Bits */

/* SVSMHCTL Control Bits */
#define SVSMHRRL0 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
#define SVSMHRRL1 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
#define SVSMHRRL2 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
#define SVSMHDLYST (0x0008u) /* SVS and SVM high side delay status */
#define SVSHMD (0x0010u) /* SVS high side mode */
#define SVSMHEVM (0x0040u) /* SVS and SVM high side event mask */
#define SVSMHACE (0x0080u) /* SVS and SVM high side auto control enable */
#define SVSHRVL0 (0x0100u) /* SVS high side reset voltage level Bit: 0 */
#define SVSHRVL1 (0x0200u) /* SVS high side reset voltage level Bit: 1 */
#define SVSHE (0x0400u) /* SVS high side enable */
#define SVSHFP (0x0800u) /* SVS high side full performace mode */
#define SVMHOVPE (0x1000u) /* SVM high side over-voltage enable */
#define SVMHE (0x4000u) /* SVM high side enable */
#define SVMHFP (0x8000u) /* SVM high side full performace mode */

/* SVSMHCTL Control Bits */
#define SVSMHRRL0_L (0x0001u) /* SVS and SVM high side Reset Release Voltage Level Bit: 0 */
#define SVSMHRRL1_L (0x0002u) /* SVS and SVM high side Reset Release Voltage Level Bit: 1 */
#define SVSMHRRL2_L (0x0004u) /* SVS and SVM high side Reset Release Voltage Level Bit: 2 */
#define SVSMHDLYST_L (0x0008u) /* SVS and SVM high side delay status */
#define SVSHMD_L (0x0010u) /* SVS high side mode */
#define SVSMHEVM_L (0x0040u) /* SVS and SVM high side event mask */
#define SVSMHACE_L (0x0080u) /* SVS and SVM high side auto control enable */

/* SVSMHCTL Control Bits */
#define SVSHRVL0_H (0x0001u) /* SVS high side reset voltage level Bit: 0 */
#define SVSHRVL1_H (0x0002u) /* SVS high side reset voltage level Bit: 1 */
#define SVSHE_H (0x0004u) /* SVS high side enable */
#define SVSHFP_H (0x0008u) /* SVS high side full performace mode */
#define SVMHOVPE_H (0x0010u) /* SVM high side over-voltage enable */
#define SVMHE_H (0x0040u) /* SVM high side enable */
#define SVMHFP_H (0x0080u) /* SVM high side full performace mode */

#define SVSMHRRL_0 (0x0000u) /* SVS and SVM high side Reset Release Voltage Level 0 */
#define SVSMHRRL_1 (0x0001u) /* SVS and SVM high side Reset Release Voltage Level 1 */
#define SVSMHRRL_2 (0x0002u) /* SVS and SVM high side Reset Release Voltage Level 2 */
#define SVSMHRRL_3 (0x0003u) /* SVS and SVM high side Reset Release Voltage Level 3 */
#define SVSMHRRL_4 (0x0004u) /* SVS and SVM high side Reset Release Voltage Level 4 */
#define SVSMHRRL_5 (0x0005u) /* SVS and SVM high side Reset Release Voltage Level 5 */
#define SVSMHRRL_6 (0x0006u) /* SVS and SVM high side Reset Release Voltage Level 6 */
#define SVSMHRRL_7 (0x0007u) /* SVS and SVM high side Reset Release Voltage Level 7 */

#define SVSHRVL_0 (0x0000u) /* SVS high side Reset Release Voltage Level 0 */
#define SVSHRVL_1 (0x0100u) /* SVS high side Reset Release Voltage Level 1 */
#define SVSHRVL_2 (0x0200u) /* SVS high side Reset Release Voltage Level 2 */
#define SVSHRVL_3 (0x0300u) /* SVS high side Reset Release Voltage Level 3 */

/* SVSMLCTL Control Bits */
#define SVSMLRRL0 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
#define SVSMLRRL1 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
#define SVSMLRRL2 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
#define SVSMLDLYST (0x0008u) /* SVS and SVM low side delay status */
#define SVSLMD (0x0010u) /* SVS low side mode */
#define SVSMLEVM (0x0040u) /* SVS and SVM low side event mask */
#define SVSMLACE (0x0080u) /* SVS and SVM low side auto control enable */
#define SVSLRVL0 (0x0100u) /* SVS low side reset voltage level Bit: 0 */
#define SVSLRVL1 (0x0200u) /* SVS low side reset voltage level Bit: 1 */
#define SVSLE (0x0400u) /* SVS low side enable */
#define SVSLFP (0x0800u) /* SVS low side full performace mode */
#define SVMLOVPE (0x1000u) /* SVM low side over-voltage enable */
#define SVMLE (0x4000u) /* SVM low side enable */
#define SVMLFP (0x8000u) /* SVM low side full performace mode */

/* SVSMLCTL Control Bits */
#define SVSMLRRL0_L (0x0001u) /* SVS and SVM low side Reset Release Voltage Level Bit: 0 */
#define SVSMLRRL1_L (0x0002u) /* SVS and SVM low side Reset Release Voltage Level Bit: 1 */
#define SVSMLRRL2_L (0x0004u) /* SVS and SVM low side Reset Release Voltage Level Bit: 2 */
#define SVSMLDLYST_L (0x0008u) /* SVS and SVM low side delay status */
#define SVSLMD_L (0x0010u) /* SVS low side mode */
#define SVSMLEVM_L (0x0040u) /* SVS and SVM low side event mask */
#define SVSMLACE_L (0x0080u) /* SVS and SVM low side auto control enable */

/* SVSMLCTL Control Bits */
#define SVSLRVL0_H (0x0001u) /* SVS low side reset voltage level Bit: 0 */
#define SVSLRVL1_H (0x0002u) /* SVS low side reset voltage level Bit: 1 */
#define SVSLE_H (0x0004u) /* SVS low side enable */
#define SVSLFP_H (0x0008u) /* SVS low side full performace mode */
#define SVMLOVPE_H (0x0010u) /* SVM low side over-voltage enable */
#define SVMLE_H (0x0040u) /* SVM low side enable */
#define SVMLFP_H (0x0080u) /* SVM low side full performace mode */

#define SVSMLRRL_0 (0x0000u) /* SVS and SVM low side Reset Release Voltage Level 0 */
#define SVSMLRRL_1 (0x0001u) /* SVS and SVM low side Reset Release Voltage Level 1 */
#define SVSMLRRL_2 (0x0002u) /* SVS and SVM low side Reset Release Voltage Level 2 */
#define SVSMLRRL_3 (0x0003u) /* SVS and SVM low side Reset Release Voltage Level 3 */
#define SVSMLRRL_4 (0x0004u) /* SVS and SVM low side Reset Release Voltage Level 4 */
#define SVSMLRRL_5 (0x0005u) /* SVS and SVM low side Reset Release Voltage Level 5 */
#define SVSMLRRL_6 (0x0006u) /* SVS and SVM low side Reset Release Voltage Level 6 */
#define SVSMLRRL_7 (0x0007u) /* SVS and SVM low side Reset Release Voltage Level 7 */

#define SVSLRVL_0 (0x0000u) /* SVS low side Reset Release Voltage Level 0 */
#define SVSLRVL_1 (0x0100u) /* SVS low side Reset Release Voltage Level 1 */
#define SVSLRVL_2 (0x0200u) /* SVS low side Reset Release Voltage Level 2 */
#define SVSLRVL_3 (0x0300u) /* SVS low side Reset Release Voltage Level 3 */

/* SVSMIO Control Bits */
#define SVMLOE (0x0008u) /* SVM low side output enable */
#define SVMLVLROE (0x0010u) /* SVM low side voltage level reached output enable */
#define SVMOUTPOL (0x0020u) /* SVMOUT pin polarity */
#define SVMHOE (0x0800u) /* SVM high side output enable */
#define SVMHVLROE (0x1000u) /* SVM high side voltage level reached output enable */

/* SVSMIO Control Bits */
#define SVMLOE_L (0x0008u) /* SVM low side output enable */
#define SVMLVLROE_L (0x0010u) /* SVM low side voltage level reached output enable */
#define SVMOUTPOL_L (0x0020u) /* SVMOUT pin polarity */

/* SVSMIO Control Bits */
#define SVMHOE_H (0x0008u) /* SVM high side output enable */
#define SVMHVLROE_H (0x0010u) /* SVM high side voltage level reached output enable */

/* PMMIFG Control Bits */
#define SVSMLDLYIFG (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */
#define SVMLIFG (0x0002u) /* SVM low side interrupt flag */
#define SVMLVLRIFG (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */
#define SVSMHDLYIFG (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */
#define SVMHIFG (0x0020u) /* SVM high side interrupt flag */
#define SVMHVLRIFG (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */
#define PMMBORIFG (0x0100u) /* PMM Software BOR interrupt flag */
#define PMMRSTIFG (0x0200u) /* PMM RESET pin interrupt flag */
#define PMMPORIFG (0x0400u) /* PMM Software POR interrupt flag */
#define SVSHIFG (0x1000u) /* SVS low side interrupt flag */
#define SVSLIFG (0x2000u) /* SVS high side interrupt flag */
#define PMMLPM5IFG (0x8000u) /* LPM5 indication Flag */

/* PMMIFG Control Bits */
#define SVSMLDLYIFG_L (0x0001u) /* SVS and SVM low side Delay expired interrupt flag */
#define SVMLIFG_L (0x0002u) /* SVM low side interrupt flag */
#define SVMLVLRIFG_L (0x0004u) /* SVM low side Voltage Level Reached interrupt flag */
#define SVSMHDLYIFG_L (0x0010u) /* SVS and SVM high side Delay expired interrupt flag */
#define SVMHIFG_L (0x0020u) /* SVM high side interrupt flag */
#define SVMHVLRIFG_L (0x0040u) /* SVM high side Voltage Level Reached interrupt flag */

/* PMMIFG Control Bits */
#define PMMBORIFG_H (0x0001u) /* PMM Software BOR interrupt flag */
#define PMMRSTIFG_H (0x0002u) /* PMM RESET pin interrupt flag */
#define PMMPORIFG_H (0x0004u) /* PMM Software POR interrupt flag */
#define SVSHIFG_H (0x0010u) /* SVS low side interrupt flag */
#define SVSLIFG_H (0x0020u) /* SVS high side interrupt flag */
#define PMMLPM5IFG_H (0x0080u) /* LPM5 indication Flag */

#define PMMRSTLPM5IFG PMMLPM5IFG /* LPM5 indication Flag */

/* PMMIE and RESET Control Bits */
#define SVSMLDLYIE (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */
#define SVMLIE (0x0002u) /* SVM low side interrupt enable */
#define SVMLVLRIE (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */
#define SVSMHDLYIE (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */
#define SVMHIE (0x0020u) /* SVM high side interrupt enable */
#define SVMHVLRIE (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */
#define SVSLPE (0x0100u) /* SVS low side POR enable */
#define SVMLVLRPE (0x0200u) /* SVM low side Voltage Level reached POR enable */
#define SVSHPE (0x1000u) /* SVS high side POR enable */
#define SVMHVLRPE (0x2000u) /* SVM high side Voltage Level reached POR enable */

/* PMMIE and RESET Control Bits */
#define SVSMLDLYIE_L (0x0001u) /* SVS and SVM low side Delay expired interrupt enable */
#define SVMLIE_L (0x0002u) /* SVM low side interrupt enable */
#define SVMLVLRIE_L (0x0004u) /* SVM low side Voltage Level Reached interrupt enable */
#define SVSMHDLYIE_L (0x0010u) /* SVS and SVM high side Delay expired interrupt enable */
#define SVMHIE_L (0x0020u) /* SVM high side interrupt enable */
#define SVMHVLRIE_L (0x0040u) /* SVM high side Voltage Level Reached interrupt enable */

/* PMMIE and RESET Control Bits */
#define SVSLPE_H (0x0001u) /* SVS low side POR enable */
#define SVMLVLRPE_H (0x0002u) /* SVM low side Voltage Level reached POR enable */
#define SVSHPE_H (0x0010u) /* SVS high side POR enable */
#define SVMHVLRPE_H (0x0020u) /* SVM high side Voltage Level reached POR enable */

/* PM5CTL0 Power Mode 5 Control Bits */
#define LOCKLPM5 (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */

/* PM5CTL0 Power Mode 5 Control Bits */
#define LOCKLPM5_L (0x0001u) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */

/* PM5CTL0 Power Mode 5 Control Bits */
#define LOCKIO LOCKLPM5 /* Lock I/O pin configuration upon entry/exit to/from LPM5 */

/*************************************************************
* RAM Control Module
*************************************************************/
#define __MSP430_HAS_RC__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_RC__ 0x0158

#define RCCTL0_ (0x0158u) /* Ram Controller Control Register */
DEFCW( RCCTL0 , RCCTL0_)

/* RCCTL0 Control Bits */
#define RCRS0OFF (0x0001u) /* RAM Controller RAM Sector 0 Off */
#define RCRS1OFF (0x0002u) /* RAM Controller RAM Sector 1 Off */
#define RCRS2OFF (0x0004u) /* RAM Controller RAM Sector 2 Off */
#define RCRS3OFF (0x0008u) /* RAM Controller RAM Sector 3 Off */

/* RCCTL0 Control Bits */
#define RCRS0OFF_L (0x0001u) /* RAM Controller RAM Sector 0 Off */
#define RCRS1OFF_L (0x0002u) /* RAM Controller RAM Sector 1 Off */
#define RCRS2OFF_L (0x0004u) /* RAM Controller RAM Sector 2 Off */
#define RCRS3OFF_L (0x0008u) /* RAM Controller RAM Sector 3 Off */

/* RCCTL0 Control Bits */

#define RCKEY (0x5A00u)

/************************************************************
* Shared Reference
************************************************************/
#define __MSP430_HAS_REF__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_REF__ 0x01B0

#define REFCTL0_ (0x01B0u) /* REF Shared Reference control register 0 */
DEFCW( REFCTL0 , REFCTL0_)

/* REFCTL0 Control Bits */
#define REFON (0x0001u) /* REF Reference On */
#define REFOUT (0x0002u) /* REF Reference output Buffer On */
//#define RESERVED (0x0004u) /* Reserved */
#define REFTCOFF (0x0008u) /* REF Temp.Sensor off */
#define REFVSEL0 (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
#define REFVSEL1 (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
//#define RESERVED (0x0040u) /* Reserved */
#define REFMSTR (0x0080u) /* REF Master Control */
#define REFGENACT (0x0100u) /* REF Reference generator active */
#define REFBGACT (0x0200u) /* REF Reference bandgap active */
#define REFGENBUSY (0x0400u) /* REF Reference generator busy */
#define BGMODE (0x0800u) /* REF Bandgap mode */
//#define RESERVED (0x1000u) /* Reserved */
//#define RESERVED (0x2000u) /* Reserved */
//#define RESERVED (0x4000u) /* Reserved */
//#define RESERVED (0x8000u) /* Reserved */

/* REFCTL0 Control Bits */
#define REFON_L (0x0001u) /* REF Reference On */
#define REFOUT_L (0x0002u) /* REF Reference output Buffer On */
//#define RESERVED (0x0004u) /* Reserved */
#define REFTCOFF_L (0x0008u) /* REF Temp.Sensor off */
#define REFVSEL0_L (0x0010u) /* REF Reference Voltage Level Select Bit:0 */
#define REFVSEL1_L (0x0020u) /* REF Reference Voltage Level Select Bit:1 */
//#define RESERVED (0x0040u) /* Reserved */
#define REFMSTR_L (0x0080u) /* REF Master Control */
//#define RESERVED (0x1000u) /* Reserved */
//#define RESERVED (0x2000u) /* Reserved */
//#define RESERVED (0x4000u) /* Reserved */
//#define RESERVED (0x8000u) /* Reserved */

/* REFCTL0 Control Bits */
//#define RESERVED (0x0004u) /* Reserved */
//#define RESERVED (0x0040u) /* Reserved */
#define REFGENACT_H (0x0001u) /* REF Reference generator active */
#define REFBGACT_H (0x0002u) /* REF Reference bandgap active */
#define REFGENBUSY_H (0x0004u) /* REF Reference generator busy */
#define BGMODE_H (0x0008u) /* REF Bandgap mode */
//#define RESERVED (0x1000u) /* Reserved */
//#define RESERVED (0x2000u) /* Reserved */
//#define RESERVED (0x4000u) /* Reserved */
//#define RESERVED (0x8000u) /* Reserved */

#define REFVSEL_0 (0x0000u) /* REF Reference Voltage Level Select 1.5V */
#define REFVSEL_1 (0x0010u) /* REF Reference Voltage Level Select 2.0V */
#define REFVSEL_2 (0x0020u) /* REF Reference Voltage Level Select 2.5V */
#define REFVSEL_3 (0x0030u) /* REF Reference Voltage Level Select 2.5V */

/************************************************************
* Real Time Clock
************************************************************/
#define __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_RTC_C__ 0x04A0

#define RTCCTL0_ (0x04A0u) /* Real Timer Clock Control 0/Key */
DEFCW( RTCCTL0 , RTCCTL0_)
#define RTCCTL13_ (0x04A2u) /* Real Timer Clock Control 1/3 */
DEFCW( RTCCTL13 , RTCCTL13_)
#define RTCCTL1 RTCCTL13_L
#define RTCCTL3 RTCCTL13_H
#define RTCOCAL_ (0x04A4u) /* Real Timer Clock Offset Calibartion */
DEFCW( RTCOCAL , RTCOCAL_)
#define RTCTCMP_ (0x04A6u) /* Real Timer Temperature Compensation */
DEFCW( RTCTCMP , RTCTCMP_)
#define RTCPS0CTL_ (0x04A8u) /* Real Timer Prescale Timer 0 Control */
DEFCW( RTCPS0CTL , RTCPS0CTL_)
#define RTCPS1CTL_ (0x04AAu) /* Real Timer Prescale Timer 1 Control */
DEFCW( RTCPS1CTL , RTCPS1CTL_)
#define RTCPS_ (0x04ACu) /* Real Timer Prescale Timer Control */
DEFCW( RTCPS , RTCPS_)
#define RTCIV_ (0x04AEu) /* Real Time Clock Interrupt Vector */
DEFW( RTCIV , RTCIV_)
#define RTCTIM0_ (0x04B0u) /* Real Time Clock Time 0 */
DEFCW( RTCTIM0 , RTCTIM0_)
#define RTCTIM1_ (0x04B2u) /* Real Time Clock Time 1 */
DEFCW( RTCTIM1 , RTCTIM1_)
#define RTCDATE_ (0x04B4u) /* Real Time Clock Date */
DEFCW( RTCDATE , RTCDATE_)
#define RTCYEAR_ (0x04B6u) /* Real Time Clock Year */
DEFCW( RTCYEAR , RTCYEAR_)
#define RTCAMINHR_ (0x04B8u) /* Real Time Clock Alarm Min/Hour */
DEFCW( RTCAMINHR , RTCAMINHR_)
#define RTCADOWDAY_ (0x04BAu) /* Real Time Clock Alarm day of week/day */
DEFCW( RTCADOWDAY , RTCADOWDAY_)
#define BIN2BCD_ (0x04BCu) /* Real Time Binary-to-BCD conversion register */
DEFW( BIN2BCD , BIN2BCD_)
#define BCD2BIN_ (0x04BEu) /* Real Time BCD-to-binary conversion register */
DEFW( BCD2BIN , BCD2BIN_)

#define RTCSEC RTCTIM0_L
#define RTCMIN RTCTIM0_H
#define RTCHOUR RTCTIM1_L
#define RTCDOW RTCTIM1_H
#define RTCDAY RTCDATE_L
#define RTCMON RTCDATE_H
#define RTCYEARL RTCYEAR_L
#define RT0PS RTCPS_L
#define RT1PS RTCPS_H
#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */

/* RTCCTL0 Control Bits */
#define RTCOFIE (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
#define RTCTEVIE (0x0040u) /* RTC Time Event Interrupt Enable Flag */
#define RTCAIE (0x0020u) /* RTC Alarm Interrupt Enable Flag */
#define RTCRDYIE (0x0010u) /* RTC Ready Interrupt Enable Flag */
#define RTCOFIFG (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
#define RTCTEVIFG (0x0004u) /* RTC Time Event Interrupt Flag */
#define RTCAIFG (0x0002u) /* RTC Alarm Interrupt Flag */
#define RTCRDYIFG (0x0001u) /* RTC Ready Interrupt Flag */

/* RTCCTL0 Control Bits */
#define RTCOFIE_L (0x0080u) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
#define RTCTEVIE_L (0x0040u) /* RTC Time Event Interrupt Enable Flag */
#define RTCAIE_L (0x0020u) /* RTC Alarm Interrupt Enable Flag */
#define RTCRDYIE_L (0x0010u) /* RTC Ready Interrupt Enable Flag */
#define RTCOFIFG_L (0x0008u) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
#define RTCTEVIFG_L (0x0004u) /* RTC Time Event Interrupt Flag */
#define RTCAIFG_L (0x0002u) /* RTC Alarm Interrupt Flag */
#define RTCRDYIFG_L (0x0001u) /* RTC Ready Interrupt Flag */

/* RTCCTL0 Control Bits */

#define RTCKEY (0xA500u) /* RTC Key for RTC write access */
#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */

/* RTCCTL13 Control Bits */
#define RTCCALF1 (0x0200u) /* RTC Calibration Frequency Bit 1 */
#define RTCCALF0 (0x0100u) /* RTC Calibration Frequency Bit 0 */
#define RTCBCD (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
#define RTCHOLD (0x0040u) /* RTC Hold */
#define RTCMODE (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
#define RTCRDY (0x0010u) /* RTC Ready */
#define RTCSSEL1 (0x0008u) /* RTC Source Select 1 */
#define RTCSSEL0 (0x0004u) /* RTC Source Select 0 */
#define RTCTEV1 (0x0002u) /* RTC Time Event 1 */
#define RTCTEV0 (0x0001u) /* RTC Time Event 0 */

/* RTCCTL13 Control Bits */
#define RTCBCD_L (0x0080u) /* RTC BCD 0:Binary / 1:BCD */
#define RTCHOLD_L (0x0040u) /* RTC Hold */
#define RTCMODE_L (0x0020u) /* RTC Mode 0:Counter / 1: Calendar */
#define RTCRDY_L (0x0010u) /* RTC Ready */
#define RTCSSEL1_L (0x0008u) /* RTC Source Select 1 */
#define RTCSSEL0_L (0x0004u) /* RTC Source Select 0 */
#define RTCTEV1_L (0x0002u) /* RTC Time Event 1 */
#define RTCTEV0_L (0x0001u) /* RTC Time Event 0 */

/* RTCCTL13 Control Bits */
#define RTCCALF1_H (0x0002u) /* RTC Calibration Frequency Bit 1 */
#define RTCCALF0_H (0x0001u) /* RTC Calibration Frequency Bit 0 */

#define RTCSSEL_0 (0x0000u) /* RTC Source Select ACLK */
#define RTCSSEL_1 (0x0004u) /* RTC Source Select SMCLK */
#define RTCSSEL_2 (0x0008u) /* RTC Source Select RT1PS */
#define RTCSSEL_3 (0x000Cu) /* RTC Source Select RT1PS */
#define RTCSSEL__ACLK (0x0000u) /* RTC Source Select ACLK */
#define RTCSSEL__SMCLK (0x0004u) /* RTC Source Select SMCLK */
#define RTCSSEL__RT1PS (0x0008u) /* RTC Source Select RT1PS */

#define RTCTEV_0 (0x0000u) /* RTC Time Event: 0 (Min. changed) */
#define RTCTEV_1 (0x0001u) /* RTC Time Event: 1 (Hour changed) */
#define RTCTEV_2 (0x0002u) /* RTC Time Event: 2 (12:00 changed) */
#define RTCTEV_3 (0x0003u) /* RTC Time Event: 3 (00:00 changed) */
#define RTCTEV__MIN (0x0000u) /* RTC Time Event: 0 (Min. changed) */
#define RTCTEV__HOUR (0x0001u) /* RTC Time Event: 1 (Hour changed) */
#define RTCTEV__0000 (0x0002u) /* RTC Time Event: 2 (00:00 changed) */
#define RTCTEV__1200 (0x0003u) /* RTC Time Event: 3 (12:00 changed) */

#define RTCCALF_0 (0x0000u) /* RTC Calibration Frequency: No Output */
#define RTCCALF_1 (0x0100u) /* RTC Calibration Frequency: 512 Hz */
#define RTCCALF_2 (0x0200u) /* RTC Calibration Frequency: 256 Hz */
#define RTCCALF_3 (0x0300u) /* RTC Calibration Frequency: 1 Hz */

/* RTCOCAL Control Bits */
#define RTCOCALS (0x8000u) /* RTC Offset Calibration Sign */
#define RTCOCAL7 (0x0080u) /* RTC Offset Calibration Bit 7 */
#define RTCOCAL6 (0x0040u) /* RTC Offset Calibration Bit 6 */
#define RTCOCAL5 (0x0020u) /* RTC Offset Calibration Bit 5 */
#define RTCOCAL4 (0x0010u) /* RTC Offset Calibration Bit 4 */
#define RTCOCAL3 (0x0008u) /* RTC Offset Calibration Bit 3 */
#define RTCOCAL2 (0x0004u) /* RTC Offset Calibration Bit 2 */
#define RTCOCAL1 (0x0002u) /* RTC Offset Calibration Bit 1 */
#define RTCOCAL0 (0x0001u) /* RTC Offset Calibration Bit 0 */

/* RTCOCAL Control Bits */
#define RTCOCAL7_L (0x0080u) /* RTC Offset Calibration Bit 7 */
#define RTCOCAL6_L (0x0040u) /* RTC Offset Calibration Bit 6 */
#define RTCOCAL5_L (0x0020u) /* RTC Offset Calibration Bit 5 */
#define RTCOCAL4_L (0x0010u) /* RTC Offset Calibration Bit 4 */
#define RTCOCAL3_L (0x0008u) /* RTC Offset Calibration Bit 3 */
#define RTCOCAL2_L (0x0004u) /* RTC Offset Calibration Bit 2 */
#define RTCOCAL1_L (0x0002u) /* RTC Offset Calibration Bit 1 */
#define RTCOCAL0_L (0x0001u) /* RTC Offset Calibration Bit 0 */

/* RTCOCAL Control Bits */
#define RTCOCALS_H (0x0080u) /* RTC Offset Calibration Sign */

/* RTCTCMP Control Bits */
#define RTCTCMPS (0x8000u) /* RTC Temperature Compensation Sign */
#define RTCTCRDY (0x4000u) /* RTC Temperature compensation ready */
#define RTCTCOK (0x2000u) /* RTC Temperature compensation write OK */
#define RTCTCMP7 (0x0080u) /* RTC Temperature Compensation Bit 7 */
#define RTCTCMP6 (0x0040u) /* RTC Temperature Compensation Bit 6 */
#define RTCTCMP5 (0x0020u) /* RTC Temperature Compensation Bit 5 */
#define RTCTCMP4 (0x0010u) /* RTC Temperature Compensation Bit 4 */
#define RTCTCMP3 (0x0008u) /* RTC Temperature Compensation Bit 3 */
#define RTCTCMP2 (0x0004u) /* RTC Temperature Compensation Bit 2 */
#define RTCTCMP1 (0x0002u) /* RTC Temperature Compensation Bit 1 */
#define RTCTCMP0 (0x0001u) /* RTC Temperature Compensation Bit 0 */

/* RTCTCMP Control Bits */
#define RTCTCMP7_L (0x0080u) /* RTC Temperature Compensation Bit 7 */
#define RTCTCMP6_L (0x0040u) /* RTC Temperature Compensation Bit 6 */
#define RTCTCMP5_L (0x0020u) /* RTC Temperature Compensation Bit 5 */
#define RTCTCMP4_L (0x0010u) /* RTC Temperature Compensation Bit 4 */
#define RTCTCMP3_L (0x0008u) /* RTC Temperature Compensation Bit 3 */
#define RTCTCMP2_L (0x0004u) /* RTC Temperature Compensation Bit 2 */
#define RTCTCMP1_L (0x0002u) /* RTC Temperature Compensation Bit 1 */
#define RTCTCMP0_L (0x0001u) /* RTC Temperature Compensation Bit 0 */

/* RTCTCMP Control Bits */
#define RTCTCMPS_H (0x0080u) /* RTC Temperature Compensation Sign */
#define RTCTCRDY_H (0x0040u) /* RTC Temperature compensation ready */
#define RTCTCOK_H (0x0020u) /* RTC Temperature compensation write OK */

/* RTCPS0CTL Control Bits */
//#define Reserved (0x0080u)
//#define Reserved (0x0040u)
//#define Reserved (0x0020u)
#define RT0IP2 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
#define RT0IP1 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
#define RT0IP0 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
#define RT0PSIE (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
#define RT0PSIFG (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */

/* RTCPS0CTL Control Bits */
//#define Reserved (0x0080u)
//#define Reserved (0x0040u)
//#define Reserved (0x0020u)
#define RT0IP2_L (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
#define RT0IP1_L (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
#define RT0IP0_L (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
#define RT0PSIE_L (0x0002u) /* RTC Prescale Timer 0 Interrupt Enable Flag */
#define RT0PSIFG_L (0x0001u) /* RTC Prescale Timer 0 Interrupt Flag */

/* RTCPS0CTL Control Bits */
//#define Reserved (0x0080u)
//#define Reserved (0x0040u)
//#define Reserved (0x0020u)

#define RT0IP_0 (0x0000u) /* RTC Prescale Timer 0 Interrupt Interval /2 */
#define RT0IP_1 (0x0004u) /* RTC Prescale Timer 0 Interrupt Interval /4 */
#define RT0IP_2 (0x0008u) /* RTC Prescale Timer 0 Interrupt Interval /8 */
#define RT0IP_3 (0x000Cu) /* RTC Prescale Timer 0 Interrupt Interval /16 */
#define RT0IP_4 (0x0010u) /* RTC Prescale Timer 0 Interrupt Interval /32 */
#define RT0IP_5 (0x0014u) /* RTC Prescale Timer 0 Interrupt Interval /64 */
#define RT0IP_6 (0x0018u) /* RTC Prescale Timer 0 Interrupt Interval /128 */
#define RT0IP_7 (0x001Cu) /* RTC Prescale Timer 0 Interrupt Interval /256 */

/* RTCPS1CTL Control Bits */
//#define Reserved (0x0080u)
//#define Reserved (0x0040u)
//#define Reserved (0x0020u)
#define RT1IP2 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
#define RT1IP1 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
#define RT1IP0 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
#define RT1PSIE (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
#define RT1PSIFG (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */

/* RTCPS1CTL Control Bits */
//#define Reserved (0x0080u)
//#define Reserved (0x0040u)
//#define Reserved (0x0020u)
#define RT1IP2_L (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
#define RT1IP1_L (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
#define RT1IP0_L (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
#define RT1PSIE_L (0x0002u) /* RTC Prescale Timer 1 Interrupt Enable Flag */
#define RT1PSIFG_L (0x0001u) /* RTC Prescale Timer 1 Interrupt Flag */

/* RTCPS1CTL Control Bits */
//#define Reserved (0x0080u)
//#define Reserved (0x0040u)
//#define Reserved (0x0020u)

#define RT1IP_0 (0x0000u) /* RTC Prescale Timer 1 Interrupt Interval /2 */
#define RT1IP_1 (0x0004u) /* RTC Prescale Timer 1 Interrupt Interval /4 */
#define RT1IP_2 (0x0008u) /* RTC Prescale Timer 1 Interrupt Interval /8 */
#define RT1IP_3 (0x000Cu) /* RTC Prescale Timer 1 Interrupt Interval /16 */
#define RT1IP_4 (0x0010u) /* RTC Prescale Timer 1 Interrupt Interval /32 */
#define RT1IP_5 (0x0014u) /* RTC Prescale Timer 1 Interrupt Interval /64 */
#define RT1IP_6 (0x0018u) /* RTC Prescale Timer 1 Interrupt Interval /128 */
#define RT1IP_7 (0x001Cu) /* RTC Prescale Timer 1 Interrupt Interval /256 */

/* RTC Definitions */
#define RTCIV_NONE (0x0000u) /* No Interrupt pending */
#define RTCIV_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
#define RTCIV_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */
#define RTCIV_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */
#define RTCIV_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */
#define RTCIV_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */
#define RTCIV_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */

/* Legacy Definitions */
#define RTC_NONE (0x0000u) /* No Interrupt pending */
#define RTC_RTCOFIFG (0x0002u) /* RTC Osc fault: RTCOFIFG */
#define RTC_RTCRDYIFG (0x0004u) /* RTC ready: RTCRDYIFG */
#define RTC_RTCTEVIFG (0x0006u) /* RTC interval timer: RTCTEVIFG */
#define RTC_RTCAIFG (0x0008u) /* RTC user alarm: RTCAIFG */
#define RTC_RT0PSIFG (0x000Au) /* RTC prescaler 0: RT0PSIFG */
#define RTC_RT1PSIFG (0x000Cu) /* RTC prescaler 1: RT1PSIFG */

/************************************************************
* SD24_B - Sigma Delta 24 Bit
************************************************************/
#define __MSP430_HAS_SD24_B__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_SD24_B__ 0x0800
#define __MSP430_HAS_SD24_B3__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_SD24_B3__ 0x0800

#define SD24BCTL0_ (0x0800u) /* SD24B Control Register 0 */
DEFCW( SD24BCTL0 , SD24BCTL0_)
#define SD24BCTL1_ (0x0802u) /* SD24B Control Register 1 */
DEFCW( SD24BCTL1 , SD24BCTL1_)
#define SD24BTRGCTL_ (0x0804u) /* SD24B Trigger Control Register */
DEFCW( SD24BTRGCTL , SD24BTRGCTL_)
#define SD24BTRGOSR_ (0x0806u) /* SD24B Trigger OSR Control Register */
DEFCW( SD24BTRGOSR , SD24BTRGOSR_)
#define SD24BTRGPRE_ (0x0808u) /* SD24B Trigger Preload Register */
DEFCW( SD24BTRGPRE , SD24BTRGPRE_)
#define SD24BIFG_ (0x080Au) /* SD24B Interrupt Flag Register */
DEFCW( SD24BIFG , SD24BIFG_)
#define SD24BIE_ (0x080Cu) /* SD24B Interrupt Enable Register */
DEFCW( SD24BIE , SD24BIE_)
#define SD24BIV_ (0x080Eu) /* SD24B Interrupt Vector Register */
DEFCW( SD24BIV , SD24BIV_)

#define SD24BCCTL0_ (0x0810u) /* SD24B Channel 0 Control Register */
DEFCW( SD24BCCTL0 , SD24BCCTL0_)
#define SD24BINCTL0_ (0x0812u) /* SD24B Channel 0 Input Control Register */
DEFCW( SD24BINCTL0 , SD24BINCTL0_)
#define SD24BOSR0_ (0x0814u) /* SD24B Channel 0 OSR Control Register */
DEFCW( SD24BOSR0 , SD24BOSR0_)
#define SD24BPRE0_ (0x0816u) /* SD24B Channel 0 Preload Register */
DEFCW( SD24BPRE0 , SD24BPRE0_)
#define SD24BCCTL1_ (0x0818u) /* SD24B Channel 1 Control Register */
DEFCW( SD24BCCTL1 , SD24BCCTL1_)
#define SD24BINCTL1_ (0x081Au) /* SD24B Channel 1 Input Control Register */
DEFCW( SD24BINCTL1 , SD24BINCTL1_)
#define SD24BOSR1_ (0x081Cu) /* SD24B Channel 1 OSR Control Register */
DEFCW( SD24BOSR1 , SD24BOSR1_)
#define SD24BPRE1_ (0x081Eu) /* SD24B Channel 1 Preload Register */
DEFCW( SD24BPRE1 , SD24BPRE1_)
#define SD24BCCTL2_ (0x0820u) /* SD24B Channel 2 Control Register */
DEFCW( SD24BCCTL2 , SD24BCCTL2_)
#define SD24BINCTL2_ (0x0822u) /* SD24B Channel 2 Input Control Register */
DEFCW( SD24BINCTL2 , SD24BINCTL2_)
#define SD24BOSR2_ (0x0824u) /* SD24B Channel 2 OSR Control Register */
DEFCW( SD24BOSR2 , SD24BOSR2_)
#define SD24BPRE2_ (0x0826u) /* SD24B Channel 2 Preload Register */
DEFCW( SD24BPRE2 , SD24BPRE2_)

#define SD24BMEML0_ (0x0850u) /* SD24B Channel 0 Conversion Memory Low word */
DEFCW( SD24BMEML0 , SD24BMEML0_)
#define SD24BMEMH0_ (0x0852u) /* SD24B Channel 0 Conversion Memory High Word */
DEFCW( SD24BMEMH0 , SD24BMEMH0_)
#define SD24BMEML1_ (0x0854u) /* SD24B Channel 1 Conversion Memory Low word */
DEFCW( SD24BMEML1 , SD24BMEML1_)
#define SD24BMEMH1_ (0x0856u) /* SD24B Channel 1 Conversion Memory High Word */
DEFCW( SD24BMEMH1 , SD24BMEMH1_)
#define SD24BMEML2_ (0x0858u) /* SD24B Channel 2 Conversion Memory Low word */
DEFCW( SD24BMEML2 , SD24BMEML2_)
#define SD24BMEMH2_ (0x085Au) /* SD24B Channel 2 Conversion Memory High Word */
DEFCW( SD24BMEMH2 , SD24BMEMH2_)

/* SD24BCTL0 */
#define SD24OV32 (0x0002u) /* SD24B Overflow Control */
#define SD24REFS (0x0004u) /* SD24B Reference Select */
#define SD24SSEL0 (0x0010u) /* SD24B Clock Source Select 0 */
#define SD24SSEL1 (0x0020u) /* SD24B Clock Source Select 1 */
#define SD24M4 (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */
#define SD24CLKOS (0x0080u) /* SD24B Clock Output Select */
#define SD24PDIV0 (0x0100u) /* SD24B Frequency pre-scaler Bit 0 */
#define SD24PDIV1 (0x0200u) /* SD24B Frequency pre-scaler Bit 1 */
#define SD24PDIV2 (0x0400u) /* SD24B Frequency pre-scaler Bit 2 */
#define SD24DIV0 (0x0800u) /* SD24B Frequency Divider Bit 0 */
#define SD24DIV1 (0x1000u) /* SD24B Frequency Divider Bit 1 */
#define SD24DIV2 (0x2000u) /* SD24B Frequency Divider Bit 2 */
#define SD24DIV3 (0x4000u) /* SD24B Frequency Divider Bit 3 */
#define SD24DIV4 (0x8000u) /* SD24B Frequency Divider Bit 4 */

#define SD24OV32_L (0x0002u) /* SD24B Overflow Control */
#define SD24REFS_L (0x0004u) /* SD24B Reference Select */
#define SD24SSEL0_L (0x0010u) /* SD24B Clock Source Select 0 */
#define SD24SSEL1_L (0x0020u) /* SD24B Clock Source Select 1 */
#define SD24M4_L (0x0040u) /* SD24B Modulator clock to Manchester decoder clock ratio */
#define SD24CLKOS_L (0x0080u) /* SD24B Clock Output Select */

#define SD24PDIV0_H (0x0001u) /* SD24B Frequency pre-scaler Bit 0 */
#define SD24PDIV1_H (0x0002u) /* SD24B Frequency pre-scaler Bit 1 */
#define SD24PDIV2_H (0x0004u) /* SD24B Frequency pre-scaler Bit 2 */
#define SD24DIV0_H (0x0008u) /* SD24B Frequency Divider Bit 0 */
#define SD24DIV1_H (0x0010u) /* SD24B Frequency Divider Bit 1 */
#define SD24DIV2_H (0x0020u) /* SD24B Frequency Divider Bit 2 */
#define SD24DIV3_H (0x0040u) /* SD24B Frequency Divider Bit 3 */
#define SD24DIV4_H (0x0080u) /* SD24B Frequency Divider Bit 4 */

#define SD24SSEL_0 (0x0000u) /* SD24B Clock Source Select MCLK */
#define SD24SSEL_1 (0x0010u) /* SD24B Clock Source Select SMCLK */
#define SD24SSEL_2 (0x0020u) /* SD24B Clock Source Select ACLK */
#define SD24SSEL_3 (0x0030u) /* SD24B Clock Source Select TACLK */
#define SD24SSEL__MCLK (0x0000u) /* SD24B Clock Source Select MCLK */
#define SD24SSEL__SMCLK (0x0010u) /* SD24B Clock Source Select SMCLK */
#define SD24SSEL__ACLK (0x0020u) /* SD24B Clock Source Select ACLK */
#define SD24SSEL__SD24CLK (0x0030u) /* SD24B Clock Source Select SD24CLK */

#define SD24PDIV_0 (0x0000u) /* SD24B Frequency pre-scaler /1 */
#define SD24PDIV_1 (0x0100u) /* SD24B Frequency pre-scaler /2 */
#define SD24PDIV_2 (0x0200u) /* SD24B Frequency pre-scaler /4 */
#define SD24PDIV_3 (0x0300u) /* SD24B Frequency pre-scaler /8 */
#define SD24PDIV_4 (0x0400u) /* SD24B Frequency pre-scaler /16 */
#define SD24PDIV_5 (0x0500u) /* SD24B Frequency pre-scaler /32 */
#define SD24PDIV_6 (0x0600u) /* SD24B Frequency pre-scaler /64 */
#define SD24PDIV_7 (0x0700u) /* SD24B Frequency pre-scaler /128 */

/* SD24BCTL1 */
#define SD24GRP0SC (0x0001u) /* SD24B Group 0 Start Conversion */
#define SD24GRP1SC (0x0002u) /* SD24B Group 1 Start Conversion */
#define SD24GRP2SC (0x0004u) /* SD24B Group 2 Start Conversion */
#define SD24GRP3SC (0x0008u) /* SD24B Group 3 Start Conversion */
#define SD24DMA0 (0x0100u) /* SD24B DMA Trigger Select Bit 0 */
#define SD24DMA1 (0x0200u) /* SD24B DMA Trigger Select Bit 1 */
#define SD24DMA2 (0x0400u) /* SD24B DMA Trigger Select Bit 2 */
#define SD24DMA3 (0x0800u) /* SD24B DMA Trigger Select Bit 3 */

#define SD24GRP0SC_L (0x0001u) /* SD24B Group 0 Start Conversion */
#define SD24GRP1SC_L (0x0002u) /* SD24B Group 1 Start Conversion */
#define SD24GRP2SC_L (0x0004u) /* SD24B Group 2 Start Conversion */
#define SD24GRP3SC_L (0x0008u) /* SD24B Group 3 Start Conversion */

#define SD24DMA0_H (0x0001u) /* SD24B DMA Trigger Select Bit 0 */
#define SD24DMA1_H (0x0002u) /* SD24B DMA Trigger Select Bit 1 */
#define SD24DMA2_H (0x0004u) /* SD24B DMA Trigger Select Bit 2 */
#define SD24DMA3_H (0x0008u) /* SD24B DMA Trigger Select Bit 3 */

#define SD24DMA_0 (0x0000u) /* SD24B DMA Trigger: 0 */
#define SD24DMA_1 (0x0100u) /* SD24B DMA Trigger: 1 */
#define SD24DMA_2 (0x0200u) /* SD24B DMA Trigger: 2 */
#define SD24DMA_3 (0x0300u) /* SD24B DMA Trigger: 3 */
#define SD24DMA_4 (0x0400u) /* SD24B DMA Trigger: 4 */
#define SD24DMA_5 (0x0500u) /* SD24B DMA Trigger: 5 */
#define SD24DMA_6 (0x0600u) /* SD24B DMA Trigger: 6 */
#define SD24DMA_7 (0x0700u) /* SD24B DMA Trigger: 7 */
#define SD24DMA_8 (0x0800u) /* SD24B DMA Trigger: 8 */

/* SD24BTRGCTL */
#define SD24SC (0x0001u) /* SD24B Start Conversion */
#define SD24SCS0 (0x0002u) /* SD24B Start Conversion Select Bit 0 */
#define SD24SCS1 (0x0004u) /* SD24B Start Conversion Select Bit 1 */
#define SD24SCS2 (0x0008u) /* SD24B Start Conversion Select Bit 2 */
#define SD24SNGL (0x0100u) /* SD24B Single Trigger Mode */
#define SD24TRGIFG (0x0400u) /* SD24B Trigger Interrupt Flag */
#define SD24TRGIE (0x0800u) /* SD24B Trigger Interrupt Enable */

#define SD24SC_L (0x0001u) /* SD24B Start Conversion */
#define SD24SCS0_L (0x0002u) /* SD24B Start Conversion Select Bit 0 */
#define SD24SCS1_L (0x0004u) /* SD24B Start Conversion Select Bit 1 */
#define SD24SCS2_L (0x0008u) /* SD24B Start Conversion Select Bit 2 */

#define SD24SNGL_H (0x0001u) /* SD24B Single Trigger Mode */
#define SD24TRGIFG_H (0x0004u) /* SD24B Trigger Interrupt Flag */
#define SD24TRGIE_H (0x0008u) /* SD24B Trigger Interrupt Enable */

#define SD24SCS_0 (0x0000u) /* SD24B Start Conversion Select: 0 */
#define SD24SCS_1 (0x0002u) /* SD24B Start Conversion Select: 1 */
#define SD24SCS_2 (0x0004u) /* SD24B Start Conversion Select: 2 */
#define SD24SCS_3 (0x0006u) /* SD24B Start Conversion Select: 3 */
#define SD24SCS_4 (0x0008u) /* SD24B Start Conversion Select: 4 */
#define SD24SCS_5 (0x000Au) /* SD24B Start Conversion Select: 5 */
#define SD24SCS_6 (0x000Cu) /* SD24B Start Conversion Select: 6 */
#define SD24SCS_7 (0x000Eu) /* SD24B Start Conversion Select: 7 */
#define SD24SCS__SD24SC (0x0000u) /* SD24B Start Conversion Select: SD24SC */
#define SD24SCS__EXT1 (0x0002u) /* SD24B Start Conversion Select: EXT1 */
#define SD24SCS__EXT2 (0x0004u) /* SD24B Start Conversion Select: EXT2 */
#define SD24SCS__EXT3 (0x0006u) /* SD24B Start Conversion Select: EXT3 */
#define SD24SCS__GROUP0 (0x0008u) /* SD24B Start Conversion Select: GROUP0 */
#define SD24SCS__GROUP1 (0x000Au) /* SD24B Start Conversion Select: GROUP1 */
#define SD24SCS__GROUP2 (0x000Cu) /* SD24B Start Conversion Select: GROUP2 */
#define SD24SCS__GROUP3 (0x000Eu) /* SD24B Start Conversion Select: GROUP3 */

/* SD24BIFG */
#define SD24IFG0 (0x0001u) /* SD24B Channel 0 Interrupt Flag */
#define SD24IFG1 (0x0002u) /* SD24B Channel 1 Interrupt Flag */
#define SD24IFG2 (0x0004u) /* SD24B Channel 2 Interrupt Flag */
#define SD24OVIFG0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Flag */
#define SD24OVIFG1 (0x0200u) /* SD24B Channel 1 Overflow Interrupt Flag */
#define SD24OVIFG2 (0x0400u) /* SD24B Channel 2 Overflow Interrupt Flag */

#define SD24IFG0_L (0x0001u) /* SD24B Channel 0 Interrupt Flag */
#define SD24IFG1_L (0x0002u) /* SD24B Channel 1 Interrupt Flag */
#define SD24IFG2_L (0x0004u) /* SD24B Channel 2 Interrupt Flag */

#define SD24OVIFG0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Flag */
#define SD24OVIFG1_H (0x0002u) /* SD24B Channel 1 Overflow Interrupt Flag */
#define SD24OVIFG2_H (0x0004u) /* SD24B Channel 2 Overflow Interrupt Flag */

/* SD24BIE */
#define SD24IE0 (0x0001u) /* SD24B Channel 0 Interrupt Enable */
#define SD24IE1 (0x0002u) /* SD24B Channel 1 Interrupt Enable */
#define SD24IE2 (0x0004u) /* SD24B Channel 2 Interrupt Enable */
#define SD24OVIE0 (0x0100u) /* SD24B Channel 0 Overflow Interrupt Enable */
#define SD24OVIE1 (0x0200u) /* SD24B Channel 1 Overflow Interrupt Enable */
#define SD24OVIE2 (0x0400u) /* SD24B Channel 2 Overflow Interrupt Enable */

#define SD24IE0_L (0x0001u) /* SD24B Channel 0 Interrupt Enable */
#define SD24IE1_L (0x0002u) /* SD24B Channel 1 Interrupt Enable */
#define SD24IE2_L (0x0004u) /* SD24B Channel 2 Interrupt Enable */

#define SD24OVIE0_H (0x0001u) /* SD24B Channel 0 Overflow Interrupt Enable */
#define SD24OVIE1_H (0x0002u) /* SD24B Channel 1 Overflow Interrupt Enable */
#define SD24OVIE2_H (0x0004u) /* SD24B Channel 2 Overflow Interrupt Enable */

/* SD24BIV Definitions */
#define SD24BIV_NONE (0x0000u) /* No Interrupt pending */
#define SD24BIV_SD24OVIFG (0x0002u) /* SD24OVIFG */
#define SD24BIV_SD24TRGIFG (0x0004u) /* SD24TRGIFG */
#define SD24BIV_SD24IFG0 (0x0006u) /* SD24IFG0 */
#define SD24BIV_SD24IFG1 (0x0008u) /* SD24IFG1 */
#define SD24BIV_SD24IFG2 (0x000Au) /* SD24IFG2 */

/* SD24BCCTLx */
#define SD24DF0 (0x0010u) /* SD24B Data Format Bit: 0 */
#define SD24DF1 (0x0020u) /* SD24B Data Format Bit: 1 */
#define SD24ALGN (0x0040u) /* SD24B Data Alignment */
#define SD24CAL (0x0200u) /* SD24B Calibration */
#define SD24DFS0 (0x0400u) /* SD24B Digital Filter Bit: 0 */
#define SD24DFS1 (0x0800u) /* SD24B Digital Filter Bit: 1 */
#define SD24DI (0x1000u) /* SD24B Digital Bitstream Input */
#define SD24MC0 (0x2000u) /* SD24B Manchaster Encoding Bit: 0 */
#define SD24MC1 (0x4000u) /* SD24B Manchaster Encoding Bit: 1 */

#define SD24DF0_L (0x0010u) /* SD24B Data Format Bit: 0 */
#define SD24DF1_L (0x0020u) /* SD24B Data Format Bit: 1 */
#define SD24ALGN_L (0x0040u) /* SD24B Data Alignment */

#define SD24CAL_H (0x0002u) /* SD24B Calibration */
#define SD24DFS0_H (0x0004u) /* SD24B Digital Filter Bit: 0 */
#define SD24DFS1_H (0x0008u) /* SD24B Digital Filter Bit: 1 */
#define SD24DI_H (0x0010u) /* SD24B Digital Bitstream Input */
#define SD24MC0_H (0x0020u) /* SD24B Manchaster Encoding Bit: 0 */
#define SD24MC1_H (0x0040u) /* SD24B Manchaster Encoding Bit: 1 */

#define SD24DF_0 (0x0000u) /* SD24B Data Format: Offset Binary */
#define SD24DF_1 (0x0010u) /* SD24B Data Format: 2's complement */

#define SD24DFS_0 (0x0000u) /* SD24B Digital Filter 0 */
#define SD24DFS_1 (0x0400u) /* SD24B Digital Filter 1 */
#define SD24DFS_2 (0x0800u) /* SD24B Digital Filter 2 */
#define SD24DFS_3 (0x0C00u) /* SD24B Digital Filter 3 */

#define SD24MC_0 (0x0000u) /* SD24B Manchaster Encoding 0 */
#define SD24MC_1 (0x2000u) /* SD24B Manchaster Encoding 1 */
#define SD24MC_2 (0x4000u) /* SD24B Manchaster Encoding 2 */
#define SD24MC_3 (0x6000u) /* SD24B Manchaster Encoding 3 */

/* SD24BINCTLx */
#define SD24INCH0 (0x0001u) /* SD24B Input Channel select 0 */
#define SD24INCH1 (0x0002u) /* SD24B Input Channel select 1 */
#define SD24INCH2 (0x0004u) /* SD24B Input Channel select 2 */
#define SD24GAIN0 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */
#define SD24GAIN1 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */
#define SD24GAIN2 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */
#define SD24INTDLY0 (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */
#define SD24INTDLY1 (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */

#define SD24INCH0_L (0x0001u) /* SD24B Input Channel select 0 */
#define SD24INCH1_L (0x0002u) /* SD24B Input Channel select 1 */
#define SD24INCH2_L (0x0004u) /* SD24B Input Channel select 2 */
#define SD24GAIN0_L (0x0008u) /* SD24B Input Pre-Amplifier Gain Select 0 */
#define SD24GAIN1_L (0x0010u) /* SD24B Input Pre-Amplifier Gain Select 1 */
#define SD24GAIN2_L (0x0020u) /* SD24B Input Pre-Amplifier Gain Select 2 */
#define SD24INTDLY0_L (0x0040u) /* SD24B Interrupt Delay after 1.Conversion 0 */
#define SD24INTDLY1_L (0x0080u) /* SD24B Interrupt Delay after 1.Conversion 1 */

#define SD24GAIN_1 (0x0000u) /* SD24B Input Pre-Amplifier Gain Select *1 */
#define SD24GAIN_2 (0x0008u) /* SD24B Input Pre-Amplifier Gain Select *2 */
#define SD24GAIN_4 (0x0010u) /* SD24B Input Pre-Amplifier Gain Select *4 */
#define SD24GAIN_8 (0x0018u) /* SD24B Input Pre-Amplifier Gain Select *8 */
#define SD24GAIN_16 (0x0020u) /* SD24B Input Pre-Amplifier Gain Select *16 */
#define SD24GAIN_32 (0x0028u) /* SD24B Input Pre-Amplifier Gain Select *32 */
#define SD24GAIN_64 (0x0030u) /* SD24B Input Pre-Amplifier Gain Select *64 */
#define SD24GAIN_128 (0x0038u) /* SD24B Input Pre-Amplifier Gain Select *128 */

#define SD24INCH_0 (0x0000u) /* SD24B Input Channel select input */
#define SD24INCH_1 (0x0001u) /* SD24B Input Channel select input */
#define SD24INCH_2 (0x0002u) /* SD24B Input Channel select input */
#define SD24INCH_3 (0x0003u) /* SD24B Input Channel select input */
#define SD24INCH_4 (0x0004u) /* SD24B Input Channel select input */
#define SD24INCH_5 (0x0005u) /* SD24B Input Channel select Vcc divider */
#define SD24INCH_6 (0x0006u) /* SD24B Input Channel select Temp */
#define SD24INCH_7 (0x0007u) /* SD24B Input Channel select Offset */

#define SD24INTDLY_0 (0x0000u) /* SD24B Interrupt Delay: Int. after 4.Conversion */
#define SD24INTDLY_1 (0x0040u) /* SD24B Interrupt Delay: Int. after 3.Conversion */
#define SD24INTDLY_2 (0x0080u) /* SD24B Interrupt Delay: Int. after 2.Conversion */
#define SD24INTDLY_3 (0x00C0u) /* SD24B Interrupt Delay: Int. after 1.Conversion */

/* SD24BOSRx */
#define OSR0 (0x0001u) /* SD24B Oversampling Rate Bit: 0 */
#define OSR1 (0x0002u) /* SD24B Oversampling Rate Bit: 1 */
#define OSR2 (0x0004u) /* SD24B Oversampling Rate Bit: 2 */
#define OSR3 (0x0008u) /* SD24B Oversampling Rate Bit: 3 */
#define OSR4 (0x0010u) /* SD24B Oversampling Rate Bit: 4 */
#define OSR5 (0x0020u) /* SD24B Oversampling Rate Bit: 5 */
#define OSR6 (0x0040u) /* SD24B Oversampling Rate Bit: 6 */
#define OSR7 (0x0080u) /* SD24B Oversampling Rate Bit: 7 */
#define OSR8 (0x0100u) /* SD24B Oversampling Rate Bit: 8 */
#define OSR9 (0x0200u) /* SD24B Oversampling Rate Bit: 9 */
#define OSR10 (0x0400u) /* SD24B Oversampling Rate Bit: 10 */

#define OSR0_L (0x0001u) /* SD24B Oversampling Rate Bit: 0 */
#define OSR1_L (0x0002u) /* SD24B Oversampling Rate Bit: 1 */
#define OSR2_L (0x0004u) /* SD24B Oversampling Rate Bit: 2 */
#define OSR3_L (0x0008u) /* SD24B Oversampling Rate Bit: 3 */
#define OSR4_L (0x0010u) /* SD24B Oversampling Rate Bit: 4 */
#define OSR5_L (0x0020u) /* SD24B Oversampling Rate Bit: 5 */
#define OSR6_L (0x0040u) /* SD24B Oversampling Rate Bit: 6 */
#define OSR7_L (0x0080u) /* SD24B Oversampling Rate Bit: 7 */

#define OSR8_H (0x0001u) /* SD24B Oversampling Rate Bit: 8 */
#define OSR9_H (0x0002u) /* SD24B Oversampling Rate Bit: 9 */
#define OSR10_H (0x0004u) /* SD24B Oversampling Rate Bit: 10 */

/* SD24BTRGOSR */

#define OSR__32 (32-1) /* SD24B Oversampling Rate: 32 */
#define OSR__64 (64-1) /* SD24B Oversampling Rate: 64 */
#define OSR__128 (128-1) /* SD24B Oversampling Rate: 128 */
#define OSR__256 (256-1) /* SD24B Oversampling Rate: 256 */
#define OSR__512 (512-1) /* SD24B Oversampling Rate: 512 */
#define OSR__1024 (1024-1) /* SD24B Oversampling Rate: 1024 */


/************************************************************
* SFR - Special Function Register Module
************************************************************/
#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_SFR__ 0x0100

#define SFRIE1_ (0x0100u) /* Interrupt Enable 1 */
DEFCW( SFRIE1 , SFRIE1_)

/* SFRIE1 Control Bits */
#define WDTIE (0x0001u) /* WDT Interrupt Enable */
#define OFIE (0x0002u) /* Osc Fault Enable */
//#define Reserved (0x0004u)
#define VMAIE (0x0008u) /* Vacant Memory Interrupt Enable */
#define NMIIE (0x0010u) /* NMI Interrupt Enable */
#define ACCVIE (0x0020u) /* Flash Access Violation Interrupt Enable */
#define JMBINIE (0x0040u) /* JTAG Mail Box input Interrupt Enable */
#define JMBOUTIE (0x0080u) /* JTAG Mail Box output Interrupt Enable */

#define WDTIE_L (0x0001u) /* WDT Interrupt Enable */
#define OFIE_L (0x0002u) /* Osc Fault Enable */
//#define Reserved (0x0004u)
#define VMAIE_L (0x0008u) /* Vacant Memory Interrupt Enable */
#define NMIIE_L (0x0010u) /* NMI Interrupt Enable */
#define ACCVIE_L (0x0020u) /* Flash Access Violation Interrupt Enable */
#define JMBINIE_L (0x0040u) /* JTAG Mail Box input Interrupt Enable */
#define JMBOUTIE_L (0x0080u) /* JTAG Mail Box output Interrupt Enable */

//#define Reserved (0x0004u)

#define SFRIFG1_ (0x0102u) /* Interrupt Flag 1 */
DEFCW( SFRIFG1 , SFRIFG1_)
/* SFRIFG1 Control Bits */
#define WDTIFG (0x0001u) /* WDT Interrupt Flag */
#define OFIFG (0x0002u) /* Osc Fault Flag */
//#define Reserved (0x0004u)
#define VMAIFG (0x0008u) /* Vacant Memory Interrupt Flag */
#define NMIIFG (0x0010u) /* NMI Interrupt Flag */
//#define Reserved (0x0020u)
#define JMBINIFG (0x0040u) /* JTAG Mail Box input Interrupt Flag */
#define JMBOUTIFG (0x0080u) /* JTAG Mail Box output Interrupt Flag */

#define WDTIFG_L (0x0001u) /* WDT Interrupt Flag */
#define OFIFG_L (0x0002u) /* Osc Fault Flag */
//#define Reserved (0x0004u)
#define VMAIFG_L (0x0008u) /* Vacant Memory Interrupt Flag */
#define NMIIFG_L (0x0010u) /* NMI Interrupt Flag */
//#define Reserved (0x0020u)
#define JMBINIFG_L (0x0040u) /* JTAG Mail Box input Interrupt Flag */
#define JMBOUTIFG_L (0x0080u) /* JTAG Mail Box output Interrupt Flag */

//#define Reserved (0x0004u)
//#define Reserved (0x0020u)

#define SFRRPCR_ (0x0104u) /* RESET Pin Control Register */
DEFCW( SFRRPCR , SFRRPCR_)
/* SFRRPCR Control Bits */
#define SYSNMI (0x0001u) /* NMI select */
#define SYSNMIIES (0x0002u) /* NMI edge select */
#define SYSRSTUP (0x0004u) /* RESET Pin pull down/up select */
#define SYSRSTRE (0x0008u) /* RESET Pin Resistor enable */

#define SYSNMI_L (0x0001u) /* NMI select */
#define SYSNMIIES_L (0x0002u) /* NMI edge select */
#define SYSRSTUP_L (0x0004u) /* RESET Pin pull down/up select */
#define SYSRSTRE_L (0x0008u) /* RESET Pin Resistor enable */

/************************************************************
* SYS - System Module
************************************************************/
#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_SYS__ 0x0180

#define SYSCTL_ (0x0180u) /* System control */
DEFCW( SYSCTL , SYSCTL_)
#define SYSBSLC_ (0x0182u) /* Boot strap configuration area */
DEFCW( SYSBSLC , SYSBSLC_)
#define SYSJMBC_ (0x0186u) /* JTAG mailbox control */
DEFCW( SYSJMBC , SYSJMBC_)
#define SYSJMBI0_ (0x0188u) /* JTAG mailbox input 0 */
DEFCW( SYSJMBI0 , SYSJMBI0_)
#define SYSJMBI1_ (0x018Au) /* JTAG mailbox input 1 */
DEFCW( SYSJMBI1 , SYSJMBI1_)
#define SYSJMBO0_ (0x018Cu) /* JTAG mailbox output 0 */
DEFCW( SYSJMBO0 , SYSJMBO0_)
#define SYSJMBO1_ (0x018Eu) /* JTAG mailbox output 1 */
DEFCW( SYSJMBO1 , SYSJMBO1_)

#define SYSBERRIV_ (0x0198u) /* Bus Error vector generator */
DEFCW( SYSBERRIV , SYSBERRIV_)
#define SYSUNIV_ (0x019Au) /* User NMI vector generator */
DEFCW( SYSUNIV , SYSUNIV_)
#define SYSSNIV_ (0x019Cu) /* System NMI vector generator */
DEFCW( SYSSNIV , SYSSNIV_)
#define SYSRSTIV_ (0x019Eu) /* Reset vector generator */
DEFCW( SYSRSTIV , SYSRSTIV_)

/* SYSCTL Control Bits */
#define SYSRIVECT (0x0001u) /* SYS - RAM based interrupt vectors */
//#define RESERVED (0x0002u) /* SYS - Reserved */
#define SYSPMMPE (0x0004u) /* SYS - PMM access protect */
//#define RESERVED (0x0008u) /* SYS - Reserved */
#define SYSBSLIND (0x0010u) /* SYS - TCK/RST indication detected */
#define SYSJTAGPIN (0x0020u) /* SYS - Dedicated JTAG pins enabled */
//#define RESERVED (0x0040u) /* SYS - Reserved */
//#define RESERVED (0x0080u) /* SYS - Reserved */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
//#define RESERVED (0x4000u) /* SYS - Reserved */
//#define RESERVED (0x8000u) /* SYS - Reserved */

/* SYSCTL Control Bits */
#define SYSRIVECT_L (0x0001u) /* SYS - RAM based interrupt vectors */
//#define RESERVED (0x0002u) /* SYS - Reserved */
#define SYSPMMPE_L (0x0004u) /* SYS - PMM access protect */
//#define RESERVED (0x0008u) /* SYS - Reserved */
#define SYSBSLIND_L (0x0010u) /* SYS - TCK/RST indication detected */
#define SYSJTAGPIN_L (0x0020u) /* SYS - Dedicated JTAG pins enabled */
//#define RESERVED (0x0040u) /* SYS - Reserved */
//#define RESERVED (0x0080u) /* SYS - Reserved */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
//#define RESERVED (0x4000u) /* SYS - Reserved */
//#define RESERVED (0x8000u) /* SYS - Reserved */

/* SYSCTL Control Bits */
//#define RESERVED (0x0002u) /* SYS - Reserved */
//#define RESERVED (0x0008u) /* SYS - Reserved */
//#define RESERVED (0x0040u) /* SYS - Reserved */
//#define RESERVED (0x0080u) /* SYS - Reserved */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
//#define RESERVED (0x4000u) /* SYS - Reserved */
//#define RESERVED (0x8000u) /* SYS - Reserved */

/* SYSBSLC Control Bits */
#define SYSBSLSIZE0 (0x0001u) /* SYS - BSL Protection Size 0 */
#define SYSBSLSIZE1 (0x0002u) /* SYS - BSL Protection Size 1 */
#define SYSBSLR (0x0004u) /* SYS - RAM assigned to BSL */
//#define RESERVED (0x0008u) /* SYS - Reserved */
//#define RESERVED (0x0010u) /* SYS - Reserved */
//#define RESERVED (0x0020u) /* SYS - Reserved */
//#define RESERVED (0x0040u) /* SYS - Reserved */
//#define RESERVED (0x0080u) /* SYS - Reserved */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
#define SYSBSLOFF (0x4000u) /* SYS - BSL Memeory disabled */
#define SYSBSLPE (0x8000u) /* SYS - BSL Memory protection enabled */

/* SYSBSLC Control Bits */
#define SYSBSLSIZE0_L (0x0001u) /* SYS - BSL Protection Size 0 */
#define SYSBSLSIZE1_L (0x0002u) /* SYS - BSL Protection Size 1 */
#define SYSBSLR_L (0x0004u) /* SYS - RAM assigned to BSL */
//#define RESERVED (0x0008u) /* SYS - Reserved */
//#define RESERVED (0x0010u) /* SYS - Reserved */
//#define RESERVED (0x0020u) /* SYS - Reserved */
//#define RESERVED (0x0040u) /* SYS - Reserved */
//#define RESERVED (0x0080u) /* SYS - Reserved */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */

/* SYSBSLC Control Bits */
//#define RESERVED (0x0008u) /* SYS - Reserved */
//#define RESERVED (0x0010u) /* SYS - Reserved */
//#define RESERVED (0x0020u) /* SYS - Reserved */
//#define RESERVED (0x0040u) /* SYS - Reserved */
//#define RESERVED (0x0080u) /* SYS - Reserved */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
#define SYSBSLOFF_H (0x0040u) /* SYS - BSL Memeory disabled */
#define SYSBSLPE_H (0x0080u) /* SYS - BSL Memory protection enabled */

/* SYSJMBC Control Bits */
#define JMBIN0FG (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */
#define JMBIN1FG (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */
#define JMBOUT0FG (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */
#define JMBOUT1FG (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */
#define JMBMODE (0x0010u) /* SYS - JMB 16/32 Bit Mode */
//#define RESERVED (0x0020u) /* SYS - Reserved */
#define JMBCLR0OFF (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
#define JMBCLR1OFF (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
//#define RESERVED (0x4000u) /* SYS - Reserved */
//#define RESERVED (0x8000u) /* SYS - Reserved */

/* SYSJMBC Control Bits */
#define JMBIN0FG_L (0x0001u) /* SYS - Incoming JTAG Mailbox 0 Flag */
#define JMBIN1FG_L (0x0002u) /* SYS - Incoming JTAG Mailbox 1 Flag */
#define JMBOUT0FG_L (0x0004u) /* SYS - Outgoing JTAG Mailbox 0 Flag */
#define JMBOUT1FG_L (0x0008u) /* SYS - Outgoing JTAG Mailbox 1 Flag */
#define JMBMODE_L (0x0010u) /* SYS - JMB 16/32 Bit Mode */
//#define RESERVED (0x0020u) /* SYS - Reserved */
#define JMBCLR0OFF_L (0x0040u) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
#define JMBCLR1OFF_L (0x0080u) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
//#define RESERVED (0x4000u) /* SYS - Reserved */
//#define RESERVED (0x8000u) /* SYS - Reserved */

/* SYSJMBC Control Bits */
//#define RESERVED (0x0020u) /* SYS - Reserved */
//#define RESERVED (0x0100u) /* SYS - Reserved */
//#define RESERVED (0x0200u) /* SYS - Reserved */
//#define RESERVED (0x0400u) /* SYS - Reserved */
//#define RESERVED (0x0800u) /* SYS - Reserved */
//#define RESERVED (0x1000u) /* SYS - Reserved */
//#define RESERVED (0x2000u) /* SYS - Reserved */
//#define RESERVED (0x4000u) /* SYS - Reserved */
//#define RESERVED (0x8000u) /* SYS - Reserved */

/* SYSUNIV Definitions */
#define SYSUNIV_NONE (0x0000u) /* No Interrupt pending */
#define SYSUNIV_NMIIFG (0x0002u) /* SYSUNIV : NMIIFG */
#define SYSUNIV_OFIFG (0x0004u) /* SYSUNIV : Osc. Fail - OFIFG */
#define SYSUNIV_ACCVIFG (0x0006u) /* SYSUNIV : Access Violation - ACCVIFG */
#define SYSUNIV_AUXSWGIFG (0x0008u) /* AUXSWGIFG : AUX supply */

/* SYSSNIV Definitions */
#define SYSSNIV_NONE (0x0000u) /* No Interrupt pending */
#define SYSSNIV_SVMLIFG (0x0002u) /* SYSSNIV : SVMLIFG */
#define SYSSNIV_SVMHIFG (0x0004u) /* SYSSNIV : SVMHIFG */
#define SYSSNIV_DLYLIFG (0x0006u) /* SYSSNIV : DLYLIFG */
#define SYSSNIV_DLYHIFG (0x0008u) /* SYSSNIV : DLYHIFG */
#define SYSSNIV_VMAIFG (0x000Au) /* SYSSNIV : VMAIFG */
#define SYSSNIV_JMBINIFG (0x000Cu) /* SYSSNIV : JMBINIFG */
#define SYSSNIV_JMBOUTIFG (0x000Eu) /* SYSSNIV : JMBOUTIFG */
#define SYSSNIV_VLRLIFG (0x0010u) /* SYSSNIV : VLRLIFG */
#define SYSSNIV_VLRHIFG (0x0012u) /* SYSSNIV : VLRHIFG */

/* SYSRSTIV Definitions */
#define SYSRSTIV_NONE (0x0000u) /* No Interrupt pending */
#define SYSRSTIV_BOR (0x0002u) /* SYSRSTIV : BOR */
#define SYSRSTIV_RSTNMI (0x0004u) /* SYSRSTIV : RST/NMI */
#define SYSRSTIV_DOBOR (0x0006u) /* SYSRSTIV : Do BOR */
#define SYSRSTIV_LPM5WU (0x0008u) /* SYSRSTIV : Port LPM5 Wake Up */
#define SYSRSTIV_SECYV (0x000Au) /* SYSRSTIV : Security violation */
#define SYSRSTIV_SVSL (0x000Cu) /* SYSRSTIV : SVSL */
#define SYSRSTIV_SVSH (0x000Eu) /* SYSRSTIV : SVSH */
#define SYSRSTIV_SVML_OVP (0x0010u) /* SYSRSTIV : SVML_OVP */
#define SYSRSTIV_SVMH_OVP (0x0012u) /* SYSRSTIV : SVMH_OVP */
#define SYSRSTIV_DOPOR (0x0014u) /* SYSRSTIV : Do POR */
#define SYSRSTIV_WDTTO (0x0016u) /* SYSRSTIV : WDT Time out */
#define SYSRSTIV_WDTKEY (0x0018u) /* SYSRSTIV : WDTKEY violation */
#define SYSRSTIV_KEYV (0x001Au) /* SYSRSTIV : Flash Key violation */
#define SYSRSTIV_FLLUL (0x001Cu) /* SYSRSTIV : FLL unlock */
#define SYSRSTIV_PERF (0x001Eu) /* SYSRSTIV : peripheral/config area fetch */
#define SYSRSTIV_PMMKEY (0x0020u) /* SYSRSTIV : PMMKEY violation */

/************************************************************
* Timer0_A3
************************************************************/
#define __MSP430_HAS_T0A3__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_T0A3__ 0x0340

#define TA0CTL_ (0x0340u) /* Timer0_A3 Control */
DEFW( TA0CTL , TA0CTL_)
#define TA0CCTL0_ (0x0342u) /* Timer0_A3 Capture/Compare Control 0 */
DEFW( TA0CCTL0 , TA0CCTL0_)
#define TA0CCTL1_ (0x0344u) /* Timer0_A3 Capture/Compare Control 1 */
DEFW( TA0CCTL1 , TA0CCTL1_)
#define TA0CCTL2_ (0x0346u) /* Timer0_A3 Capture/Compare Control 2 */
DEFW( TA0CCTL2 , TA0CCTL2_)
#define TA0R_ (0x0350u) /* Timer0_A3 */
DEFW( TA0R , TA0R_)
#define TA0CCR0_ (0x0352u) /* Timer0_A3 Capture/Compare 0 */
DEFW( TA0CCR0 , TA0CCR0_)
#define TA0CCR1_ (0x0354u) /* Timer0_A3 Capture/Compare 1 */
DEFW( TA0CCR1 , TA0CCR1_)
#define TA0CCR2_ (0x0356u) /* Timer0_A3 Capture/Compare 2 */
DEFW( TA0CCR2 , TA0CCR2_)
#define TA0IV_ (0x036Eu) /* Timer0_A3 Interrupt Vector Word */
DEFW( TA0IV , TA0IV_)
#define TA0EX0_ (0x0360u) /* Timer0_A3 Expansion Register 0 */
DEFW( TA0EX0 , TA0EX0_)

/* TAxCTL Control Bits */
#define TASSEL1 (0x0200u) /* Timer A clock source select 1 */
#define TASSEL0 (0x0100u) /* Timer A clock source select 0 */
#define ID1 (0x0080u) /* Timer A clock input divider 1 */
#define ID0 (0x0040u) /* Timer A clock input divider 0 */
#define MC1 (0x0020u) /* Timer A mode control 1 */
#define MC0 (0x0010u) /* Timer A mode control 0 */
#define TACLR (0x0004u) /* Timer A counter clear */
#define TAIE (0x0002u) /* Timer A counter interrupt enable */
#define TAIFG (0x0001u) /* Timer A counter interrupt flag */

#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */
#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continuous up */
#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */
#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */
#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */
#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */
#define MC__STOP (0*0x10u) /* Timer A mode control: 0 - Stop */
#define MC__UP (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */
#define MC__CONTINUOUS (2*0x10u) /* Timer A mode control: 2 - Continuous up */
#define MC__CONTINOUS (2*0x10u) /* Legacy define */
#define MC__UPDOWN (3*0x10u) /* Timer A mode control: 3 - Up/Down */
#define ID__1 (0*0x40u) /* Timer A input divider: 0 - /1 */
#define ID__2 (1*0x40u) /* Timer A input divider: 1 - /2 */
#define ID__4 (2*0x40u) /* Timer A input divider: 2 - /4 */
#define ID__8 (3*0x40u) /* Timer A input divider: 3 - /8 */
#define TASSEL__TACLK (0*0x100u) /* Timer A clock source select: 0 - TACLK */
#define TASSEL__ACLK (1*0x100u) /* Timer A clock source select: 1 - ACLK */
#define TASSEL__SMCLK (2*0x100u) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL__INCLK (3*0x100u) /* Timer A clock source select: 3 - INCLK */

/* TAxCCTLx Control Bits */
#define CM1 (0x8000u) /* Capture mode 1 */
#define CM0 (0x4000u) /* Capture mode 0 */
#define CCIS1 (0x2000u) /* Capture input select 1 */
#define CCIS0 (0x1000u) /* Capture input select 0 */
#define SCS (0x0800u) /* Capture sychronize */
#define SCCI (0x0400u) /* Latched capture signal (read) */
#define CAP (0x0100u) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080u) /* Output mode 2 */
#define OUTMOD1 (0x0040u) /* Output mode 1 */
#define OUTMOD0 (0x0020u) /* Output mode 0 */
#define CCIE (0x0010u) /* Capture/compare interrupt enable */
#define CCI (0x0008u) /* Capture input signal (read) */
#define OUT (0x0004u) /* PWM Output signal if output mode 0 */
#define COV (0x0002u) /* Capture/compare overflow flag */
#define CCIFG (0x0001u) /* Capture/compare interrupt flag */

#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */
#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */
#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */
#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */
#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */
#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */
#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */

/* TAxEX0 Control Bits */
#define TAIDEX0 (0x0001u) /* Timer A Input divider expansion Bit: 0 */
#define TAIDEX1 (0x0002u) /* Timer A Input divider expansion Bit: 1 */
#define TAIDEX2 (0x0004u) /* Timer A Input divider expansion Bit: 2 */

#define TAIDEX_0 (0*0x0001u) /* Timer A Input divider expansion : /1 */
#define TAIDEX_1 (1*0x0001u) /* Timer A Input divider expansion : /2 */
#define TAIDEX_2 (2*0x0001u) /* Timer A Input divider expansion : /3 */
#define TAIDEX_3 (3*0x0001u) /* Timer A Input divider expansion : /4 */
#define TAIDEX_4 (4*0x0001u) /* Timer A Input divider expansion : /5 */
#define TAIDEX_5 (5*0x0001u) /* Timer A Input divider expansion : /6 */
#define TAIDEX_6 (6*0x0001u) /* Timer A Input divider expansion : /7 */
#define TAIDEX_7 (7*0x0001u) /* Timer A Input divider expansion : /8 */

/* T0A3IV Definitions */
#define TA0IV_NONE (0x0000u) /* No Interrupt pending */
#define TA0IV_TA0CCR1 (0x0002u) /* TA0CCR1_CCIFG */
#define TA0IV_TA0CCR2 (0x0004u) /* TA0CCR2_CCIFG */
#define TA0IV_3 (0x0006u) /* Reserved */
#define TA0IV_4 (0x0008u) /* Reserved */
#define TA0IV_5 (0x000Au) /* Reserved */
#define TA0IV_6 (0x000Cu) /* Reserved */
#define TA0IV_TA0IFG (0x000Eu) /* TA0IFG */

/************************************************************
* Timer1_A2
************************************************************/
#define __MSP430_HAS_T1A2__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_T1A2__ 0x0380

#define TA1CTL_ (0x0380u) /* Timer1_A2 Control */
DEFW( TA1CTL , TA1CTL_)
#define TA1CCTL0_ (0x0382u) /* Timer1_A2 Capture/Compare Control 0 */
DEFW( TA1CCTL0 , TA1CCTL0_)
#define TA1CCTL1_ (0x0384u) /* Timer1_A2 Capture/Compare Control 1 */
DEFW( TA1CCTL1 , TA1CCTL1_)
#define TA1R_ (0x0390u) /* Timer1_A2 */
DEFW( TA1R , TA1R_)
#define TA1CCR0_ (0x0392u) /* Timer1_A2 Capture/Compare 0 */
DEFW( TA1CCR0 , TA1CCR0_)
#define TA1CCR1_ (0x0394u) /* Timer1_A2 Capture/Compare 1 */
DEFW( TA1CCR1 , TA1CCR1_)
#define TA1IV_ (0x03AEu) /* Timer1_A2 Interrupt Vector Word */
DEFW( TA1IV , TA1IV_)
#define TA1EX0_ (0x03A0u) /* Timer1_A2 Expansion Register 0 */
DEFW( TA1EX0 , TA1EX0_)

/* Bits are already defined within the Timer0_Ax */

/* TA1IV Definitions */
#define TA1IV_NONE (0x0000u) /* No Interrupt pending */
#define TA1IV_TA1CCR1 (0x0002u) /* TA1CCR1_CCIFG */
#define TA1IV_3 (0x0006u) /* Reserved */
#define TA1IV_4 (0x0008u) /* Reserved */
#define TA1IV_5 (0x000Au) /* Reserved */
#define TA1IV_6 (0x000Cu) /* Reserved */
#define TA1IV_TA1IFG (0x000Eu) /* TA1IFG */

/************************************************************
* Timer2_A2
************************************************************/
#define __MSP430_HAS_T2A2__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_T2A2__ 0x0400

#define TA2CTL_ (0x0400u) /* Timer2_A2 Control */
DEFW( TA2CTL , TA2CTL_)
#define TA2CCTL0_ (0x0402u) /* Timer2_A2 Capture/Compare Control 0 */
DEFW( TA2CCTL0 , TA2CCTL0_)
#define TA2CCTL1_ (0x0404u) /* Timer2_A2 Capture/Compare Control 1 */
DEFW( TA2CCTL1 , TA2CCTL1_)
#define TA2R_ (0x0410u) /* Timer2_A2 */
DEFW( TA2R , TA2R_)
#define TA2CCR0_ (0x0412u) /* Timer2_A2 Capture/Compare 0 */
DEFW( TA2CCR0 , TA2CCR0_)
#define TA2CCR1_ (0x0414u) /* Timer2_A2 Capture/Compare 1 */
DEFW( TA2CCR1 , TA2CCR1_)
#define TA2IV_ (0x042Eu) /* Timer2_A2 Interrupt Vector Word */
DEFW( TA2IV , TA2IV_)
#define TA2EX0_ (0x0420u) /* Timer2_A2 Expansion Register 0 */
DEFW( TA2EX0 , TA2EX0_)

/* Bits are already defined within the Timer0_Ax */

/* TA2IV Definitions */
#define TA2IV_NONE (0x0000u) /* No Interrupt pending */
#define TA2IV_TA1CCR1 (0x0002u) /* TA2CCR1_CCIFG */
#define TA2IV_3 (0x0006u) /* Reserved */
#define TA2IV_4 (0x0008u) /* Reserved */
#define TA2IV_5 (0x000Au) /* Reserved */
#define TA2IV_6 (0x000Cu) /* Reserved */
#define TA2IV_TA2IFG (0x000Eu) /* TA2IFG */

/************************************************************
* Timer3_A2
************************************************************/
#define __MSP430_HAS_T3A2__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_T3A2__ 0x0440

#define TA3CTL_ (0x0440u) /* Timer3_A2 Control */
DEFW( TA3CTL , TA3CTL_)
#define TA3CCTL0_ (0x0442u) /* Timer3_A2 Capture/Compare Control 0 */
DEFW( TA3CCTL0 , TA3CCTL0_)
#define TA3CCTL1_ (0x0444u) /* Timer3_A2 Capture/Compare Control 1 */
DEFW( TA3CCTL1 , TA3CCTL1_)
#define TA3R_ (0x0450u) /* Timer3_A2 */
DEFW( TA3R , TA3R_)
#define TA3CCR0_ (0x0452u) /* Timer3_A2 Capture/Compare 0 */
DEFW( TA3CCR0 , TA3CCR0_)
#define TA3CCR1_ (0x0454u) /* Timer3_A2 Capture/Compare 1 */
DEFW( TA3CCR1 , TA3CCR1_)
#define TA3IV_ (0x046Eu) /* Timer3_A2 Interrupt Vector Word */
DEFW( TA3IV , TA3IV_)
#define TA3EX0_ (0x0460u) /* Timer3_A2 Expansion Register 0 */
DEFW( TA3EX0 , TA3EX0_)

/* Bits are already defined within the Timer0_Ax */

/* TA3IV Definitions */
#define TA3IV_NONE (0x0000u) /* No Interrupt pending */
#define TA3IV_TA1CCR1 (0x0002u) /* TA3CCR1_CCIFG */
#define TA3IV_3 (0x0006u) /* Reserved */
#define TA3IV_4 (0x0008u) /* Reserved */
#define TA3IV_5 (0x000Au) /* Reserved */
#define TA3IV_6 (0x000Cu) /* Reserved */
#define TA3IV_TA3IFG (0x000Eu) /* TA3IFG */

/************************************************************
* UNIFIED CLOCK SYSTEM
************************************************************/
#define __MSP430_HAS_UCS__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_UCS__ 0x0160

#define UCSCTL0_ (0x0160u) /* UCS Control Register 0 */
DEFCW( UCSCTL0 , UCSCTL0_)
#define UCSCTL1_ (0x0162u) /* UCS Control Register 1 */
DEFCW( UCSCTL1 , UCSCTL1_)
#define UCSCTL2_ (0x0164u) /* UCS Control Register 2 */
DEFCW( UCSCTL2 , UCSCTL2_)
#define UCSCTL3_ (0x0166u) /* UCS Control Register 3 */
DEFCW( UCSCTL3 , UCSCTL3_)
#define UCSCTL4_ (0x0168u) /* UCS Control Register 4 */
DEFCW( UCSCTL4 , UCSCTL4_)
#define UCSCTL5_ (0x016Au) /* UCS Control Register 5 */
DEFCW( UCSCTL5 , UCSCTL5_)
#define UCSCTL6_ (0x016Cu) /* UCS Control Register 6 */
DEFCW( UCSCTL6 , UCSCTL6_)
#define UCSCTL7_ (0x016Eu) /* UCS Control Register 7 */
DEFCW( UCSCTL7 , UCSCTL7_)
#define UCSCTL8_ (0x0170u) /* UCS Control Register 8 */
DEFCW( UCSCTL8 , UCSCTL8_)

/* UCSCTL0 Control Bits */
//#define RESERVED (0x0001u) /* RESERVED */
//#define RESERVED (0x0002u) /* RESERVED */
//#define RESERVED (0x0004u) /* RESERVED */
#define MOD0 (0x0008u) /* Modulation Bit Counter Bit : 0 */
#define MOD1 (0x0010u) /* Modulation Bit Counter Bit : 1 */
#define MOD2 (0x0020u) /* Modulation Bit Counter Bit : 2 */
#define MOD3 (0x0040u) /* Modulation Bit Counter Bit : 3 */
#define MOD4 (0x0080u) /* Modulation Bit Counter Bit : 4 */
#define DCO0 (0x0100u) /* DCO TAP Bit : 0 */
#define DCO1 (0x0200u) /* DCO TAP Bit : 1 */
#define DCO2 (0x0400u) /* DCO TAP Bit : 2 */
#define DCO3 (0x0800u) /* DCO TAP Bit : 3 */
#define DCO4 (0x1000u) /* DCO TAP Bit : 4 */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL0 Control Bits */
//#define RESERVED (0x0001u) /* RESERVED */
//#define RESERVED (0x0002u) /* RESERVED */
//#define RESERVED (0x0004u) /* RESERVED */
#define MOD0_L (0x0008u) /* Modulation Bit Counter Bit : 0 */
#define MOD1_L (0x0010u) /* Modulation Bit Counter Bit : 1 */
#define MOD2_L (0x0020u) /* Modulation Bit Counter Bit : 2 */
#define MOD3_L (0x0040u) /* Modulation Bit Counter Bit : 3 */
#define MOD4_L (0x0080u) /* Modulation Bit Counter Bit : 4 */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL0 Control Bits */
//#define RESERVED (0x0001u) /* RESERVED */
//#define RESERVED (0x0002u) /* RESERVED */
//#define RESERVED (0x0004u) /* RESERVED */
#define DCO0_H (0x0001u) /* DCO TAP Bit : 0 */
#define DCO1_H (0x0002u) /* DCO TAP Bit : 1 */
#define DCO2_H (0x0004u) /* DCO TAP Bit : 2 */
#define DCO3_H (0x0008u) /* DCO TAP Bit : 3 */
#define DCO4_H (0x0010u) /* DCO TAP Bit : 4 */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL1 Control Bits */
#define DISMOD (0x0001u) /* Disable Modulation */
//#define RESERVED (0x0002u) /* RESERVED */
//#define RESERVED (0x0004u) /* RESERVED */
//#define RESERVED (0x0008u) /* RESERVED */
#define DCORSEL0 (0x0010u) /* DCO Freq. Range Select Bit : 0 */
#define DCORSEL1 (0x0020u) /* DCO Freq. Range Select Bit : 1 */
#define DCORSEL2 (0x0040u) /* DCO Freq. Range Select Bit : 2 */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL1 Control Bits */
#define DISMOD_L (0x0001u) /* Disable Modulation */
//#define RESERVED (0x0002u) /* RESERVED */
//#define RESERVED (0x0004u) /* RESERVED */
//#define RESERVED (0x0008u) /* RESERVED */
#define DCORSEL0_L (0x0010u) /* DCO Freq. Range Select Bit : 0 */
#define DCORSEL1_L (0x0020u) /* DCO Freq. Range Select Bit : 1 */
#define DCORSEL2_L (0x0040u) /* DCO Freq. Range Select Bit : 2 */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL1 Control Bits */
//#define RESERVED (0x0002u) /* RESERVED */
//#define RESERVED (0x0004u) /* RESERVED */
//#define RESERVED (0x0008u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

#define DCORSEL_0 (0x0000u) /* DCO RSEL 0 */
#define DCORSEL_1 (0x0010u) /* DCO RSEL 1 */
#define DCORSEL_2 (0x0020u) /* DCO RSEL 2 */
#define DCORSEL_3 (0x0030u) /* DCO RSEL 3 */
#define DCORSEL_4 (0x0040u) /* DCO RSEL 4 */
#define DCORSEL_5 (0x0050u) /* DCO RSEL 5 */
#define DCORSEL_6 (0x0060u) /* DCO RSEL 6 */
#define DCORSEL_7 (0x0070u) /* DCO RSEL 7 */

/* UCSCTL2 Control Bits */
#define FLLN0 (0x0001u) /* FLL Multipier Bit : 0 */
#define FLLN1 (0x0002u) /* FLL Multipier Bit : 1 */
#define FLLN2 (0x0004u) /* FLL Multipier Bit : 2 */
#define FLLN3 (0x0008u) /* FLL Multipier Bit : 3 */
#define FLLN4 (0x0010u) /* FLL Multipier Bit : 4 */
#define FLLN5 (0x0020u) /* FLL Multipier Bit : 5 */
#define FLLN6 (0x0040u) /* FLL Multipier Bit : 6 */
#define FLLN7 (0x0080u) /* FLL Multipier Bit : 7 */
#define FLLN8 (0x0100u) /* FLL Multipier Bit : 8 */
#define FLLN9 (0x0200u) /* FLL Multipier Bit : 9 */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
#define FLLD0 (0x1000u) /* Loop Divider Bit : 0 */
#define FLLD1 (0x2000u) /* Loop Divider Bit : 1 */
#define FLLD2 (0x4000u) /* Loop Divider Bit : 1 */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL2 Control Bits */
#define FLLN0_L (0x0001u) /* FLL Multipier Bit : 0 */
#define FLLN1_L (0x0002u) /* FLL Multipier Bit : 1 */
#define FLLN2_L (0x0004u) /* FLL Multipier Bit : 2 */
#define FLLN3_L (0x0008u) /* FLL Multipier Bit : 3 */
#define FLLN4_L (0x0010u) /* FLL Multipier Bit : 4 */
#define FLLN5_L (0x0020u) /* FLL Multipier Bit : 5 */
#define FLLN6_L (0x0040u) /* FLL Multipier Bit : 6 */
#define FLLN7_L (0x0080u) /* FLL Multipier Bit : 7 */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL2 Control Bits */
#define FLLN8_H (0x0001u) /* FLL Multipier Bit : 8 */
#define FLLN9_H (0x0002u) /* FLL Multipier Bit : 9 */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
#define FLLD0_H (0x0010u) /* Loop Divider Bit : 0 */
#define FLLD1_H (0x0020u) /* Loop Divider Bit : 1 */
#define FLLD2_H (0x0040u) /* Loop Divider Bit : 1 */
//#define RESERVED (0x8000u) /* RESERVED */

#define FLLD_0 (0x0000u) /* Multiply Selected Loop Freq. 1 */
#define FLLD_1 (0x1000u) /* Multiply Selected Loop Freq. 2 */
#define FLLD_2 (0x2000u) /* Multiply Selected Loop Freq. 4 */
#define FLLD_3 (0x3000u) /* Multiply Selected Loop Freq. 8 */
#define FLLD_4 (0x4000u) /* Multiply Selected Loop Freq. 16 */
#define FLLD_5 (0x5000u) /* Multiply Selected Loop Freq. 32 */
#define FLLD_6 (0x6000u) /* Multiply Selected Loop Freq. 32 */
#define FLLD_7 (0x7000u) /* Multiply Selected Loop Freq. 32 */
#define FLLD__1 (0x0000u) /* Multiply Selected Loop Freq. By 1 */
#define FLLD__2 (0x1000u) /* Multiply Selected Loop Freq. By 2 */
#define FLLD__4 (0x2000u) /* Multiply Selected Loop Freq. By 4 */
#define FLLD__8 (0x3000u) /* Multiply Selected Loop Freq. By 8 */
#define FLLD__16 (0x4000u) /* Multiply Selected Loop Freq. By 16 */
#define FLLD__32 (0x5000u) /* Multiply Selected Loop Freq. By 32 */

/* UCSCTL3 Control Bits */
#define FLLREFDIV0 (0x0001u) /* Reference Divider Bit : 0 */
#define FLLREFDIV1 (0x0002u) /* Reference Divider Bit : 1 */
#define FLLREFDIV2 (0x0004u) /* Reference Divider Bit : 2 */
//#define RESERVED (0x0008u) /* RESERVED */
#define SELREF0 (0x0010u) /* FLL Reference Clock Select Bit : 0 */
#define SELREF1 (0x0020u) /* FLL Reference Clock Select Bit : 1 */
#define SELREF2 (0x0040u) /* FLL Reference Clock Select Bit : 2 */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL3 Control Bits */
#define FLLREFDIV0_L (0x0001u) /* Reference Divider Bit : 0 */
#define FLLREFDIV1_L (0x0002u) /* Reference Divider Bit : 1 */
#define FLLREFDIV2_L (0x0004u) /* Reference Divider Bit : 2 */
//#define RESERVED (0x0008u) /* RESERVED */
#define SELREF0_L (0x0010u) /* FLL Reference Clock Select Bit : 0 */
#define SELREF1_L (0x0020u) /* FLL Reference Clock Select Bit : 1 */
#define SELREF2_L (0x0040u) /* FLL Reference Clock Select Bit : 2 */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL3 Control Bits */
//#define RESERVED (0x0008u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

#define FLLREFDIV_0 (0x0000u) /* Reference Divider: f(LFCLK)/1 */
#define FLLREFDIV_1 (0x0001u) /* Reference Divider: f(LFCLK)/2 */
#define FLLREFDIV_2 (0x0002u) /* Reference Divider: f(LFCLK)/4 */
#define FLLREFDIV_3 (0x0003u) /* Reference Divider: f(LFCLK)/8 */
#define FLLREFDIV_4 (0x0004u) /* Reference Divider: f(LFCLK)/12 */
#define FLLREFDIV_5 (0x0005u) /* Reference Divider: f(LFCLK)/16 */
#define FLLREFDIV_6 (0x0006u) /* Reference Divider: f(LFCLK)/16 */
#define FLLREFDIV_7 (0x0007u) /* Reference Divider: f(LFCLK)/16 */
#define FLLREFDIV__1 (0x0000u) /* Reference Divider: f(LFCLK)/1 */
#define FLLREFDIV__2 (0x0001u) /* Reference Divider: f(LFCLK)/2 */
#define FLLREFDIV__4 (0x0002u) /* Reference Divider: f(LFCLK)/4 */
#define FLLREFDIV__8 (0x0003u) /* Reference Divider: f(LFCLK)/8 */
#define FLLREFDIV__12 (0x0004u) /* Reference Divider: f(LFCLK)/12 */
#define FLLREFDIV__16 (0x0005u) /* Reference Divider: f(LFCLK)/16 */
#define SELREF_0 (0x0000u) /* FLL Reference Clock Select 0 */
#define SELREF_1 (0x0010u) /* FLL Reference Clock Select 1 */
#define SELREF_2 (0x0020u) /* FLL Reference Clock Select 2 */
#define SELREF_3 (0x0030u) /* FLL Reference Clock Select 3 */
#define SELREF_4 (0x0040u) /* FLL Reference Clock Select 4 */
#define SELREF_5 (0x0050u) /* FLL Reference Clock Select 5 */
#define SELREF_6 (0x0060u) /* FLL Reference Clock Select 6 */
#define SELREF_7 (0x0070u) /* FLL Reference Clock Select 7 */
#define SELREF__XT1CLK (0x0000u) /* Multiply Selected Loop Freq. By XT1CLK */
#define SELREF__REFOCLK (0x0020u) /* Multiply Selected Loop Freq. By REFOCLK */
#define SELREF__XT2CLK (0x0050u) /* Multiply Selected Loop Freq. By XT2CLK */

/* UCSCTL4 Control Bits */
#define SELM0 (0x0001u) /* MCLK Source Select Bit: 0 */
#define SELM1 (0x0002u) /* MCLK Source Select Bit: 1 */
#define SELM2 (0x0004u) /* MCLK Source Select Bit: 2 */
//#define RESERVED (0x0008u) /* RESERVED */
#define SELS0 (0x0010u) /* SMCLK Source Select Bit: 0 */
#define SELS1 (0x0020u) /* SMCLK Source Select Bit: 1 */
#define SELS2 (0x0040u) /* SMCLK Source Select Bit: 2 */
//#define RESERVED (0x0080u) /* RESERVED */
#define SELA0 (0x0100u) /* ACLK Source Select Bit: 0 */
#define SELA1 (0x0200u) /* ACLK Source Select Bit: 1 */
#define SELA2 (0x0400u) /* ACLK Source Select Bit: 2 */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL4 Control Bits */
#define SELM0_L (0x0001u) /* MCLK Source Select Bit: 0 */
#define SELM1_L (0x0002u) /* MCLK Source Select Bit: 1 */
#define SELM2_L (0x0004u) /* MCLK Source Select Bit: 2 */
//#define RESERVED (0x0008u) /* RESERVED */
#define SELS0_L (0x0010u) /* SMCLK Source Select Bit: 0 */
#define SELS1_L (0x0020u) /* SMCLK Source Select Bit: 1 */
#define SELS2_L (0x0040u) /* SMCLK Source Select Bit: 2 */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL4 Control Bits */
//#define RESERVED (0x0008u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
#define SELA0_H (0x0001u) /* ACLK Source Select Bit: 0 */
#define SELA1_H (0x0002u) /* ACLK Source Select Bit: 1 */
#define SELA2_H (0x0004u) /* ACLK Source Select Bit: 2 */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

#define SELM_0 (0x0000u) /* MCLK Source Select 0 */
#define SELM_1 (0x0001u) /* MCLK Source Select 1 */
#define SELM_2 (0x0002u) /* MCLK Source Select 2 */
#define SELM_3 (0x0003u) /* MCLK Source Select 3 */
#define SELM_4 (0x0004u) /* MCLK Source Select 4 */
#define SELM_5 (0x0005u) /* MCLK Source Select 5 */
#define SELM_6 (0x0006u) /* MCLK Source Select 6 */
#define SELM_7 (0x0007u) /* MCLK Source Select 7 */
#define SELM__XT1CLK (0x0000u) /* MCLK Source Select XT1CLK */
#define SELM__VLOCLK (0x0001u) /* MCLK Source Select VLOCLK */
#define SELM__REFOCLK (0x0002u) /* MCLK Source Select REFOCLK */
#define SELM__DCOCLK (0x0003u) /* MCLK Source Select DCOCLK */
#define SELM__DCOCLKDIV (0x0004u) /* MCLK Source Select DCOCLKDIV */
#define SELM__XT2CLK (0x0005u) /* MCLK Source Select XT2CLK */

#define SELS_0 (0x0000u) /* SMCLK Source Select 0 */
#define SELS_1 (0x0010u) /* SMCLK Source Select 1 */
#define SELS_2 (0x0020u) /* SMCLK Source Select 2 */
#define SELS_3 (0x0030u) /* SMCLK Source Select 3 */
#define SELS_4 (0x0040u) /* SMCLK Source Select 4 */
#define SELS_5 (0x0050u) /* SMCLK Source Select 5 */
#define SELS_6 (0x0060u) /* SMCLK Source Select 6 */
#define SELS_7 (0x0070u) /* SMCLK Source Select 7 */
#define SELS__XT1CLK (0x0000u) /* SMCLK Source Select XT1CLK */
#define SELS__VLOCLK (0x0010u) /* SMCLK Source Select VLOCLK */
#define SELS__REFOCLK (0x0020u) /* SMCLK Source Select REFOCLK */
#define SELS__DCOCLK (0x0030u) /* SMCLK Source Select DCOCLK */
#define SELS__DCOCLKDIV (0x0040u) /* SMCLK Source Select DCOCLKDIV */
#define SELS__XT2CLK (0x0050u) /* SMCLK Source Select XT2CLK */

#define SELA_0 (0x0000u) /* ACLK Source Select 0 */
#define SELA_1 (0x0100u) /* ACLK Source Select 1 */
#define SELA_2 (0x0200u) /* ACLK Source Select 2 */
#define SELA_3 (0x0300u) /* ACLK Source Select 3 */
#define SELA_4 (0x0400u) /* ACLK Source Select 4 */
#define SELA_5 (0x0500u) /* ACLK Source Select 5 */
#define SELA_6 (0x0600u) /* ACLK Source Select 6 */
#define SELA_7 (0x0700u) /* ACLK Source Select 7 */
#define SELA__XT1CLK (0x0000u) /* ACLK Source Select XT1CLK */
#define SELA__VLOCLK (0x0100u) /* ACLK Source Select VLOCLK */
#define SELA__REFOCLK (0x0200u) /* ACLK Source Select REFOCLK */
#define SELA__DCOCLK (0x0300u) /* ACLK Source Select DCOCLK */
#define SELA__DCOCLKDIV (0x0400u) /* ACLK Source Select DCOCLKDIV */
#define SELA__XT2CLK (0x0500u) /* ACLK Source Select XT2CLK */

/* UCSCTL5 Control Bits */
#define DIVM0 (0x0001u) /* MCLK Divider Bit: 0 */
#define DIVM1 (0x0002u) /* MCLK Divider Bit: 1 */
#define DIVM2 (0x0004u) /* MCLK Divider Bit: 2 */
//#define RESERVED (0x0008u) /* RESERVED */
#define DIVS0 (0x0010u) /* SMCLK Divider Bit: 0 */
#define DIVS1 (0x0020u) /* SMCLK Divider Bit: 1 */
#define DIVS2 (0x0040u) /* SMCLK Divider Bit: 2 */
//#define RESERVED (0x0080u) /* RESERVED */
#define DIVA0 (0x0100u) /* ACLK Divider Bit: 0 */
#define DIVA1 (0x0200u) /* ACLK Divider Bit: 1 */
#define DIVA2 (0x0400u) /* ACLK Divider Bit: 2 */
//#define RESERVED (0x0800u) /* RESERVED */
#define DIVPA0 (0x1000u) /* ACLK from Pin Divider Bit: 0 */
#define DIVPA1 (0x2000u) /* ACLK from Pin Divider Bit: 1 */
#define DIVPA2 (0x4000u) /* ACLK from Pin Divider Bit: 2 */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL5 Control Bits */
#define DIVM0_L (0x0001u) /* MCLK Divider Bit: 0 */
#define DIVM1_L (0x0002u) /* MCLK Divider Bit: 1 */
#define DIVM2_L (0x0004u) /* MCLK Divider Bit: 2 */
//#define RESERVED (0x0008u) /* RESERVED */
#define DIVS0_L (0x0010u) /* SMCLK Divider Bit: 0 */
#define DIVS1_L (0x0020u) /* SMCLK Divider Bit: 1 */
#define DIVS2_L (0x0040u) /* SMCLK Divider Bit: 2 */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL5 Control Bits */
//#define RESERVED (0x0008u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
#define DIVA0_H (0x0001u) /* ACLK Divider Bit: 0 */
#define DIVA1_H (0x0002u) /* ACLK Divider Bit: 1 */
#define DIVA2_H (0x0004u) /* ACLK Divider Bit: 2 */
//#define RESERVED (0x0800u) /* RESERVED */
#define DIVPA0_H (0x0010u) /* ACLK from Pin Divider Bit: 0 */
#define DIVPA1_H (0x0020u) /* ACLK from Pin Divider Bit: 1 */
#define DIVPA2_H (0x0040u) /* ACLK from Pin Divider Bit: 2 */
//#define RESERVED (0x8000u) /* RESERVED */

#define DIVM_0 (0x0000u) /* MCLK Source Divider 0 */
#define DIVM_1 (0x0001u) /* MCLK Source Divider 1 */
#define DIVM_2 (0x0002u) /* MCLK Source Divider 2 */
#define DIVM_3 (0x0003u) /* MCLK Source Divider 3 */
#define DIVM_4 (0x0004u) /* MCLK Source Divider 4 */
#define DIVM_5 (0x0005u) /* MCLK Source Divider 5 */
#define DIVM_6 (0x0006u) /* MCLK Source Divider 6 */
#define DIVM_7 (0x0007u) /* MCLK Source Divider 7 */
#define DIVM__1 (0x0000u) /* MCLK Source Divider f(MCLK)/1 */
#define DIVM__2 (0x0001u) /* MCLK Source Divider f(MCLK)/2 */
#define DIVM__4 (0x0002u) /* MCLK Source Divider f(MCLK)/4 */
#define DIVM__8 (0x0003u) /* MCLK Source Divider f(MCLK)/8 */
#define DIVM__16 (0x0004u) /* MCLK Source Divider f(MCLK)/16 */
#define DIVM__32 (0x0005u) /* MCLK Source Divider f(MCLK)/32 */

#define DIVS_0 (0x0000u) /* SMCLK Source Divider 0 */
#define DIVS_1 (0x0010u) /* SMCLK Source Divider 1 */
#define DIVS_2 (0x0020u) /* SMCLK Source Divider 2 */
#define DIVS_3 (0x0030u) /* SMCLK Source Divider 3 */
#define DIVS_4 (0x0040u) /* SMCLK Source Divider 4 */
#define DIVS_5 (0x0050u) /* SMCLK Source Divider 5 */
#define DIVS_6 (0x0060u) /* SMCLK Source Divider 6 */
#define DIVS_7 (0x0070u) /* SMCLK Source Divider 7 */
#define DIVS__1 (0x0000u) /* SMCLK Source Divider f(SMCLK)/1 */
#define DIVS__2 (0x0010u) /* SMCLK Source Divider f(SMCLK)/2 */
#define DIVS__4 (0x0020u) /* SMCLK Source Divider f(SMCLK)/4 */
#define DIVS__8 (0x0030u) /* SMCLK Source Divider f(SMCLK)/8 */
#define DIVS__16 (0x0040u) /* SMCLK Source Divider f(SMCLK)/16 */
#define DIVS__32 (0x0050u) /* SMCLK Source Divider f(SMCLK)/32 */

#define DIVA_0 (0x0000u) /* ACLK Source Divider 0 */
#define DIVA_1 (0x0100u) /* ACLK Source Divider 1 */
#define DIVA_2 (0x0200u) /* ACLK Source Divider 2 */
#define DIVA_3 (0x0300u) /* ACLK Source Divider 3 */
#define DIVA_4 (0x0400u) /* ACLK Source Divider 4 */
#define DIVA_5 (0x0500u) /* ACLK Source Divider 5 */
#define DIVA_6 (0x0600u) /* ACLK Source Divider 6 */
#define DIVA_7 (0x0700u) /* ACLK Source Divider 7 */
#define DIVA__1 (0x0000u) /* ACLK Source Divider f(ACLK)/1 */
#define DIVA__2 (0x0100u) /* ACLK Source Divider f(ACLK)/2 */
#define DIVA__4 (0x0200u) /* ACLK Source Divider f(ACLK)/4 */
#define DIVA__8 (0x0300u) /* ACLK Source Divider f(ACLK)/8 */
#define DIVA__16 (0x0400u) /* ACLK Source Divider f(ACLK)/16 */
#define DIVA__32 (0x0500u) /* ACLK Source Divider f(ACLK)/32 */

#define DIVPA_0 (0x0000u) /* ACLK from Pin Source Divider 0 */
#define DIVPA_1 (0x1000u) /* ACLK from Pin Source Divider 1 */
#define DIVPA_2 (0x2000u) /* ACLK from Pin Source Divider 2 */
#define DIVPA_3 (0x3000u) /* ACLK from Pin Source Divider 3 */
#define DIVPA_4 (0x4000u) /* ACLK from Pin Source Divider 4 */
#define DIVPA_5 (0x5000u) /* ACLK from Pin Source Divider 5 */
#define DIVPA_6 (0x6000u) /* ACLK from Pin Source Divider 6 */
#define DIVPA_7 (0x7000u) /* ACLK from Pin Source Divider 7 */
#define DIVPA__1 (0x0000u) /* ACLK from Pin Source Divider f(ACLK)/1 */
#define DIVPA__2 (0x1000u) /* ACLK from Pin Source Divider f(ACLK)/2 */
#define DIVPA__4 (0x2000u) /* ACLK from Pin Source Divider f(ACLK)/4 */
#define DIVPA__8 (0x3000u) /* ACLK from Pin Source Divider f(ACLK)/8 */
#define DIVPA__16 (0x4000u) /* ACLK from Pin Source Divider f(ACLK)/16 */
#define DIVPA__32 (0x5000u) /* ACLK from Pin Source Divider f(ACLK)/32 */

/* UCSCTL6 Control Bits */
#define XT1OFF (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
#define SMCLKOFF (0x0002u) /* SMCLK Off */
#define XCAP0 (0x0004u) /* XIN/XOUT Cap Bit: 0 */
#define XCAP1 (0x0008u) /* XIN/XOUT Cap Bit: 1 */
#define XT1BYPASS (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
#define XTS (0x0020u) /* 1: Selects high-freq. oscillator */
#define XT1DRIVE0 (0x0040u) /* XT1 Drive Level mode Bit 0 */
#define XT1DRIVE1 (0x0080u) /* XT1 Drive Level mode Bit 1 */
#define XT2OFF (0x0100u) /* High Frequency Oscillator 2 (XT2) disable */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
#define XT2BYPASS (0x1000u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
//#define RESERVED (0x2000u) /* RESERVED */
#define XT2DRIVE0 (0x4000u) /* XT2 Drive Level mode Bit 0 */
#define XT2DRIVE1 (0x8000u) /* XT2 Drive Level mode Bit 1 */

/* UCSCTL6 Control Bits */
#define XT1OFF_L (0x0001u) /* High Frequency Oscillator 1 (XT1) disable */
#define SMCLKOFF_L (0x0002u) /* SMCLK Off */
#define XCAP0_L (0x0004u) /* XIN/XOUT Cap Bit: 0 */
#define XCAP1_L (0x0008u) /* XIN/XOUT Cap Bit: 1 */
#define XT1BYPASS_L (0x0010u) /* XT1 bypass mode : 0: internal 1:sourced from external pin */
#define XTS_L (0x0020u) /* 1: Selects high-freq. oscillator */
#define XT1DRIVE0_L (0x0040u) /* XT1 Drive Level mode Bit 0 */
#define XT1DRIVE1_L (0x0080u) /* XT1 Drive Level mode Bit 1 */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */

/* UCSCTL6 Control Bits */
#define XT2OFF_H (0x0001u) /* High Frequency Oscillator 2 (XT2) disable */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
#define XT2BYPASS_H (0x0010u) /* XT2 bypass mode : 0: internal 1:sourced from external pin */
//#define RESERVED (0x2000u) /* RESERVED */
#define XT2DRIVE0_H (0x0040u) /* XT2 Drive Level mode Bit 0 */
#define XT2DRIVE1_H (0x0080u) /* XT2 Drive Level mode Bit 1 */

#define XCAP_0 (0x0000u) /* XIN/XOUT Cap 0 */
#define XCAP_1 (0x0004u) /* XIN/XOUT Cap 1 */
#define XCAP_2 (0x0008u) /* XIN/XOUT Cap 2 */
#define XCAP_3 (0x000Cu) /* XIN/XOUT Cap 3 */
#define XT1DRIVE_0 (0x0000u) /* XT1 Drive Level mode: 0 */
#define XT1DRIVE_1 (0x0040u) /* XT1 Drive Level mode: 1 */
#define XT1DRIVE_2 (0x0080u) /* XT1 Drive Level mode: 2 */
#define XT1DRIVE_3 (0x00C0u) /* XT1 Drive Level mode: 3 */
#define XT2DRIVE_0 (0x0000u) /* XT2 Drive Level mode: 0 */
#define XT2DRIVE_1 (0x4000u) /* XT2 Drive Level mode: 1 */
#define XT2DRIVE_2 (0x8000u) /* XT2 Drive Level mode: 2 */
#define XT2DRIVE_3 (0xC000u) /* XT2 Drive Level mode: 3 */

/* UCSCTL7 Control Bits */
#define DCOFFG (0x0001u) /* DCO Fault Flag */
#define XT1LFOFFG (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */
//#define RESERVED (0x0004u) /* RESERVED */
#define XT2OFFG (0x0008u) /* High Frequency Oscillator 2 Fault Flag */
//#define RESERVED (0x0010u) /* RESERVED */
//#define RESERVED (0x0020u) /* RESERVED */
//#define RESERVED (0x0040u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL7 Control Bits */
#define DCOFFG_L (0x0001u) /* DCO Fault Flag */
#define XT1LFOFFG_L (0x0002u) /* XT1 Low Frequency Oscillator Fault Flag */
//#define RESERVED (0x0004u) /* RESERVED */
#define XT2OFFG_L (0x0008u) /* High Frequency Oscillator 2 Fault Flag */
//#define RESERVED (0x0010u) /* RESERVED */
//#define RESERVED (0x0020u) /* RESERVED */
//#define RESERVED (0x0040u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL7 Control Bits */
//#define RESERVED (0x0004u) /* RESERVED */
//#define RESERVED (0x0010u) /* RESERVED */
//#define RESERVED (0x0020u) /* RESERVED */
//#define RESERVED (0x0040u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL8 Control Bits */
#define ACLKREQEN (0x0001u) /* ACLK Clock Request Enable */
#define MCLKREQEN (0x0002u) /* MCLK Clock Request Enable */
#define SMCLKREQEN (0x0004u) /* SMCLK Clock Request Enable */
#define MODOSCREQEN (0x0008u) /* MODOSC Clock Request Enable */
//#define RESERVED (0x0010u) /* RESERVED */
//#define RESERVED (0x0020u) /* RESERVED */
//#define RESERVED (0x0040u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL8 Control Bits */
#define ACLKREQEN_L (0x0001u) /* ACLK Clock Request Enable */
#define MCLKREQEN_L (0x0002u) /* MCLK Clock Request Enable */
#define SMCLKREQEN_L (0x0004u) /* SMCLK Clock Request Enable */
#define MODOSCREQEN_L (0x0008u) /* MODOSC Clock Request Enable */
//#define RESERVED (0x0010u) /* RESERVED */
//#define RESERVED (0x0020u) /* RESERVED */
//#define RESERVED (0x0040u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/* UCSCTL8 Control Bits */
//#define RESERVED (0x0010u) /* RESERVED */
//#define RESERVED (0x0020u) /* RESERVED */
//#define RESERVED (0x0040u) /* RESERVED */
//#define RESERVED (0x0080u) /* RESERVED */
//#define RESERVED (0x0100u) /* RESERVED */
//#define RESERVED (0x0200u) /* RESERVED */
//#define RESERVED (0x0400u) /* RESERVED */
//#define RESERVED (0x0800u) /* RESERVED */
//#define RESERVED (0x1000u) /* RESERVED */
//#define RESERVED (0x2000u) /* RESERVED */
//#define RESERVED (0x4000u) /* RESERVED */
//#define RESERVED (0x8000u) /* RESERVED */

/************************************************************
* USCI A0
************************************************************/
#define __MSP430_HAS_EUSCI_A0__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x05C0

#define UCA0CTLW0_ (0x05C0u) /* USCI A0 Control Word Register 0 */
DEFCW( UCA0CTLW0 , UCA0CTLW0_)
#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
#define UCA0CTLW1_ (0x05C2u) /* USCI A0 Control Word Register 1 */
DEFCW( UCA0CTLW1 , UCA0CTLW1_)
#define UCA0BRW_ (0x05C6u) /* USCI A0 Baud Word Rate 0 */
DEFCW( UCA0BRW , UCA0BRW_)
#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
#define UCA0MCTLW_ (0x05C8u) /* USCI A0 Modulation Control */
DEFCW( UCA0MCTLW , UCA0MCTLW_)
#define UCA0STATW_ (0x05CAu) /* USCI A0 Status Register */
DEFC( UCA0STATW , UCA0STATW_)
#define UCA0RXBUF_ (0x05CCu) /* USCI A0 Receive Buffer */
READ_ONLY_DEFCW( UCA0RXBUF , UCA0RXBUF_)
#define UCA0TXBUF_ (0x05CEu) /* USCI A0 Transmit Buffer */
DEFCW( UCA0TXBUF , UCA0TXBUF_)
#define UCA0ABCTL_ (0x05D0u) /* USCI A0 LIN Control */
DEFC( UCA0ABCTL , UCA0ABCTL_)
#define UCA0IRCTL_ (0x05D2u) /* USCI A0 IrDA Transmit Control */
DEFCW( UCA0IRCTL , UCA0IRCTL_)
#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
#define UCA0IE_ (0x05DAu) /* USCI A0 Interrupt Enable Register */
DEFCW( UCA0IE , UCA0IE_)
#define UCA0IFG_ (0x05DCu) /* USCI A0 Interrupt Flags Register */
DEFCW( UCA0IFG , UCA0IFG_)
#define UCA0IV_ (0x05DEu) /* USCI A0 Interrupt Vector Register */
DEFW( UCA0IV , UCA0IV_)


/************************************************************
* USCI B0
************************************************************/
#define __MSP430_HAS_EUSCI_B0__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0640


#define UCB0CTLW0_ (0x0640u) /* USCI B0 Control Word Register 0 */
DEFCW( UCB0CTLW0 , UCB0CTLW0_)
#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
#define UCB0CTLW1_ (0x0642u) /* USCI B0 Control Word Register 1 */
DEFCW( UCB0CTLW1 , UCB0CTLW1_)
#define UCB0BRW_ (0x0646u) /* USCI B0 Baud Word Rate 0 */
DEFCW( UCB0BRW , UCB0BRW_)
#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
#define UCB0STATW_ (0x0648u) /* USCI B0 Status Word Register */
DEFCW( UCB0STATW , UCB0STATW_)
#define UCB0STAT UCB0STATW_L /* USCI B0 Status Register */
#define UCB0BCNT UCB0STATW_H /* USCI B0 Byte Counter Register */
#define UCB0TBCNT_ (0x064Au) /* USCI B0 Byte Counter Threshold Register */
DEFCW( UCB0TBCNT , UCB0TBCNT_)
#define UCB0RXBUF_ (0x064Cu) /* USCI B0 Receive Buffer */
READ_ONLY_DEFCW( UCB0RXBUF , UCB0RXBUF_)
#define UCB0TXBUF_ (0x064Eu) /* USCI B0 Transmit Buffer */
DEFCW( UCB0TXBUF , UCB0TXBUF_)
#define UCB0I2COA0_ (0x0654u) /* USCI B0 I2C Own Address 0 */
DEFCW( UCB0I2COA0 , UCB0I2COA0_)
#define UCB0I2COA1_ (0x0656u) /* USCI B0 I2C Own Address 1 */
DEFCW( UCB0I2COA1 , UCB0I2COA1_)
#define UCB0I2COA2_ (0x0658u) /* USCI B0 I2C Own Address 2 */
DEFCW( UCB0I2COA2 , UCB0I2COA2_)
#define UCB0I2COA3_ (0x065Au) /* USCI B0 I2C Own Address 3 */
DEFCW( UCB0I2COA3 , UCB0I2COA3_)
#define UCB0ADDRX_ (0x065Cu) /* USCI B0 Received Address Register */
DEFCW( UCB0ADDRX , UCB0ADDRX_)
#define UCB0ADDMASK_ (0x065Eu) /* USCI B0 Address Mask Register */
DEFCW( UCB0ADDMASK , UCB0ADDMASK_)
#define UCB0I2CSA_ (0x0660u) /* USCI B0 I2C Slave Address */
DEFCW( UCB0I2CSA , UCB0I2CSA_)
#define UCB0IE_ (0x066Au) /* USCI B0 Interrupt Enable Register */
DEFCW( UCB0IE , UCB0IE_)
#define UCB0IFG_ (0x066Cu) /* USCI B0 Interrupt Flags Register */
DEFCW( UCB0IFG , UCB0IFG_)
#define UCB0IV_ (0x066Eu) /* USCI B0 Interrupt Vector Register */
DEFW( UCB0IV , UCB0IV_)

// UCAxCTLW0 UART-Mode Control Bits
#define UCPEN (0x8000u) /* Async. Mode: Parity enable */
#define UCPAR (0x4000u) /* Async. Mode: Parity 0:odd / 1:even */
#define UCMSB (0x2000u) /* Async. Mode: MSB first 0:LSB / 1:MSB */
#define UC7BIT (0x1000u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
#define UCSPB (0x0800u) /* Async. Mode: Stop Bits 0:one / 1: two */
#define UCMODE1 (0x0400u) /* Async. Mode: USCI Mode 1 */
#define UCMODE0 (0x0200u) /* Async. Mode: USCI Mode 0 */
#define UCSYNC (0x0100u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
#define UCSSEL1 (0x0080u) /* USCI 0 Clock Source Select 1 */
#define UCSSEL0 (0x0040u) /* USCI 0 Clock Source Select 0 */
#define UCRXEIE (0x0020u) /* RX Error interrupt enable */
#define UCBRKIE (0x0010u) /* Break interrupt enable */
#define UCDORM (0x0008u) /* Dormant (Sleep) Mode */
#define UCTXADDR (0x0004u) /* Send next Data as Address */
#define UCTXBRK (0x0002u) /* Send next Data as Break */
#define UCSWRST (0x0001u) /* USCI Software Reset */

// UCAxCTLW0 UART-Mode Control Bits
#define UCSSEL1_L (0x0080u) /* USCI 0 Clock Source Select 1 */
#define UCSSEL0_L (0x0040u) /* USCI 0 Clock Source Select 0 */
#define UCRXEIE_L (0x0020u) /* RX Error interrupt enable */
#define UCBRKIE_L (0x0010u) /* Break interrupt enable */
#define UCDORM_L (0x0008u) /* Dormant (Sleep) Mode */
#define UCTXADDR_L (0x0004u) /* Send next Data as Address */
#define UCTXBRK_L (0x0002u) /* Send next Data as Break */
#define UCSWRST_L (0x0001u) /* USCI Software Reset */

// UCAxCTLW0 UART-Mode Control Bits
#define UCPEN_H (0x0080u) /* Async. Mode: Parity enable */
#define UCPAR_H (0x0040u) /* Async. Mode: Parity 0:odd / 1:even */
#define UCMSB_H (0x0020u) /* Async. Mode: MSB first 0:LSB / 1:MSB */
#define UC7BIT_H (0x0010u) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
#define UCSPB_H (0x0008u) /* Async. Mode: Stop Bits 0:one / 1: two */
#define UCMODE1_H (0x0004u) /* Async. Mode: USCI Mode 1 */
#define UCMODE0_H (0x0002u) /* Async. Mode: USCI Mode 0 */
#define UCSYNC_H (0x0001u) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */

// UCxxCTLW0 SPI-Mode Control Bits
#define UCCKPH (0x8000u) /* Sync. Mode: Clock Phase */
#define UCCKPL (0x4000u) /* Sync. Mode: Clock Polarity */
#define UCMST (0x0800u) /* Sync. Mode: Master Select */
//#define res (0x0020u) /* reserved */
//#define res (0x0010u) /* reserved */
//#define res (0x0008u) /* reserved */
//#define res (0x0004u) /* reserved */
#define UCSTEM (0x0002u) /* USCI STE Mode */

// UCBxCTLW0 I2C-Mode Control Bits
#define UCA10 (0x8000u) /* 10-bit Address Mode */
#define UCSLA10 (0x4000u) /* 10-bit Slave Address Mode */
#define UCMM (0x2000u) /* Multi-Master Environment */
//#define res (0x1000u) /* reserved */
//#define res (0x0100u) /* reserved */
#define UCTXACK (0x0020u) /* Transmit ACK */
#define UCTR (0x0010u) /* Transmit/Receive Select/Flag */
#define UCTXNACK (0x0008u) /* Transmit NACK */
#define UCTXSTP (0x0004u) /* Transmit STOP */
#define UCTXSTT (0x0002u) /* Transmit START */

// UCBxCTLW0 I2C-Mode Control Bits
//#define res (0x1000u) /* reserved */
//#define res (0x0100u) /* reserved */
#define UCTXACK_L (0x0020u) /* Transmit ACK */
#define UCTR_L (0x0010u) /* Transmit/Receive Select/Flag */
#define UCTXNACK_L (0x0008u) /* Transmit NACK */
#define UCTXSTP_L (0x0004u) /* Transmit STOP */
#define UCTXSTT_L (0x0002u) /* Transmit START */

// UCBxCTLW0 I2C-Mode Control Bits
#define UCA10_H (0x0080u) /* 10-bit Address Mode */
#define UCSLA10_H (0x0040u) /* 10-bit Slave Address Mode */
#define UCMM_H (0x0020u) /* Multi-Master Environment */
//#define res (0x1000u) /* reserved */
//#define res (0x0100u) /* reserved */

#define UCMODE_0 (0x0000u) /* Sync. Mode: USCI Mode: 0 */
#define UCMODE_1 (0x0200u) /* Sync. Mode: USCI Mode: 1 */
#define UCMODE_2 (0x0400u) /* Sync. Mode: USCI Mode: 2 */
#define UCMODE_3 (0x0600u) /* Sync. Mode: USCI Mode: 3 */

#define UCSSEL_0 (0x0000u) /* USCI 0 Clock Source: 0 */
#define UCSSEL_1 (0x0040u) /* USCI 0 Clock Source: 1 */
#define UCSSEL_2 (0x0080u) /* USCI 0 Clock Source: 2 */
#define UCSSEL_3 (0x00C0u) /* USCI 0 Clock Source: 3 */
#define UCSSEL__UCLK (0x0000u) /* USCI 0 Clock Source: UCLK */
#define UCSSEL__ACLK (0x0040u) /* USCI 0 Clock Source: ACLK */
#define UCSSEL__SMCLK (0x0080u) /* USCI 0 Clock Source: SMCLK */

// UCAxCTLW1 UART-Mode Control Bits
#define UCGLIT1 (0x0002u) /* USCI Deglitch Time Bit 1 */
#define UCGLIT0 (0x0001u) /* USCI Deglitch Time Bit 0 */

// UCAxCTLW1 UART-Mode Control Bits
#define UCGLIT1_L (0x0002u) /* USCI Deglitch Time Bit 1 */
#define UCGLIT0_L (0x0001u) /* USCI Deglitch Time Bit 0 */

// UCAxCTLW1 UART-Mode Control Bits

// UCBxCTLW1 I2C-Mode Control Bits
#define UCETXINT (0x0100u) /* USCI Early UCTXIFG0 */
#define UCCLTO1 (0x0080u) /* USCI Clock low timeout Bit: 1 */
#define UCCLTO0 (0x0040u) /* USCI Clock low timeout Bit: 0 */
#define UCSTPNACK (0x0020u) /* USCI Acknowledge Stop last byte */
#define UCSWACK (0x0010u) /* USCI Software controlled ACK */
#define UCASTP1 (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */
#define UCASTP0 (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */
#define UCGLIT1 (0x0002u) /* USCI Deglitch time Bit: 1 */
#define UCGLIT0 (0x0001u) /* USCI Deglitch time Bit: 0 */

// UCBxCTLW1 I2C-Mode Control Bits
#define UCCLTO1_L (0x0080u) /* USCI Clock low timeout Bit: 1 */
#define UCCLTO0_L (0x0040u) /* USCI Clock low timeout Bit: 0 */
#define UCSTPNACK_L (0x0020u) /* USCI Acknowledge Stop last byte */
#define UCSWACK_L (0x0010u) /* USCI Software controlled ACK */
#define UCASTP1_L (0x0008u) /* USCI Automatic Stop condition generation Bit: 1 */
#define UCASTP0_L (0x0004u) /* USCI Automatic Stop condition generation Bit: 0 */
#define UCGLIT1_L (0x0002u) /* USCI Deglitch time Bit: 1 */
#define UCGLIT0_L (0x0001u) /* USCI Deglitch time Bit: 0 */

// UCBxCTLW1 I2C-Mode Control Bits
#define UCETXINT_H (0x0001u) /* USCI Early UCTXIFG0 */

#define UCGLIT_0 (0x0000u) /* USCI Deglitch time: 0 */
#define UCGLIT_1 (0x0001u) /* USCI Deglitch time: 1 */
#define UCGLIT_2 (0x0002u) /* USCI Deglitch time: 2 */
#define UCGLIT_3 (0x0003u) /* USCI Deglitch time: 3 */

#define UCASTP_0 (0x0000u) /* USCI Automatic Stop condition generation: 0 */
#define UCASTP_1 (0x0004u) /* USCI Automatic Stop condition generation: 1 */
#define UCASTP_2 (0x0008u) /* USCI Automatic Stop condition generation: 2 */
#define UCASTP_3 (0x000Cu) /* USCI Automatic Stop condition generation: 3 */

#define UCCLTO_0 (0x0000u) /* USCI Clock low timeout: 0 */
#define UCCLTO_1 (0x0040u) /* USCI Clock low timeout: 1 */
#define UCCLTO_2 (0x0080u) /* USCI Clock low timeout: 2 */
#define UCCLTO_3 (0x00C0u) /* USCI Clock low timeout: 3 */

/* UCAxMCTLW Control Bits */
#define UCBRS7 (0x8000u) /* USCI Second Stage Modulation Select 7 */
#define UCBRS6 (0x4000u) /* USCI Second Stage Modulation Select 6 */
#define UCBRS5 (0x2000u) /* USCI Second Stage Modulation Select 5 */
#define UCBRS4 (0x1000u) /* USCI Second Stage Modulation Select 4 */
#define UCBRS3 (0x0800u) /* USCI Second Stage Modulation Select 3 */
#define UCBRS2 (0x0400u) /* USCI Second Stage Modulation Select 2 */
#define UCBRS1 (0x0200u) /* USCI Second Stage Modulation Select 1 */
#define UCBRS0 (0x0100u) /* USCI Second Stage Modulation Select 0 */
#define UCBRF3 (0x0080u) /* USCI First Stage Modulation Select 3 */
#define UCBRF2 (0x0040u) /* USCI First Stage Modulation Select 2 */
#define UCBRF1 (0x0020u) /* USCI First Stage Modulation Select 1 */
#define UCBRF0 (0x0010u) /* USCI First Stage Modulation Select 0 */
#define UCOS16 (0x0001u) /* USCI 16-times Oversampling enable */

/* UCAxMCTLW Control Bits */
#define UCBRF3_L (0x0080u) /* USCI First Stage Modulation Select 3 */
#define UCBRF2_L (0x0040u) /* USCI First Stage Modulation Select 2 */
#define UCBRF1_L (0x0020u) /* USCI First Stage Modulation Select 1 */
#define UCBRF0_L (0x0010u) /* USCI First Stage Modulation Select 0 */
#define UCOS16_L (0x0001u) /* USCI 16-times Oversampling enable */

/* UCAxMCTLW Control Bits */
#define UCBRS7_H (0x0080u) /* USCI Second Stage Modulation Select 7 */
#define UCBRS6_H (0x0040u) /* USCI Second Stage Modulation Select 6 */
#define UCBRS5_H (0x0020u) /* USCI Second Stage Modulation Select 5 */
#define UCBRS4_H (0x0010u) /* USCI Second Stage Modulation Select 4 */
#define UCBRS3_H (0x0008u) /* USCI Second Stage Modulation Select 3 */
#define UCBRS2_H (0x0004u) /* USCI Second Stage Modulation Select 2 */
#define UCBRS1_H (0x0002u) /* USCI Second Stage Modulation Select 1 */
#define UCBRS0_H (0x0001u) /* USCI Second Stage Modulation Select 0 */

#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */

/* UCAxSTATW Control Bits */
#define UCLISTEN (0x0080u) /* USCI Listen mode */
#define UCFE (0x0040u) /* USCI Frame Error Flag */
#define UCOE (0x0020u) /* USCI Overrun Error Flag */
#define UCPE (0x0010u) /* USCI Parity Error Flag */
#define UCBRK (0x0008u) /* USCI Break received */
#define UCRXERR (0x0004u) /* USCI RX Error Flag */
#define UCADDR (0x0002u) /* USCI Address received Flag */
#define UCBUSY (0x0001u) /* USCI Busy Flag */
#define UCIDLE (0x0002u) /* USCI Idle line detected Flag */

/* UCBxSTATW I2C Control Bits */
#define UCBCNT7 (0x8000u) /* USCI Byte Counter Bit 7 */
#define UCBCNT6 (0x4000u) /* USCI Byte Counter Bit 6 */
#define UCBCNT5 (0x2000u) /* USCI Byte Counter Bit 5 */
#define UCBCNT4 (0x1000u) /* USCI Byte Counter Bit 4 */
#define UCBCNT3 (0x0800u) /* USCI Byte Counter Bit 3 */
#define UCBCNT2 (0x0400u) /* USCI Byte Counter Bit 2 */
#define UCBCNT1 (0x0200u) /* USCI Byte Counter Bit 1 */
#define UCBCNT0 (0x0100u) /* USCI Byte Counter Bit 0 */
#define UCSCLLOW (0x0040u) /* SCL low */
#define UCGC (0x0020u) /* General Call address received Flag */
#define UCBBUSY (0x0010u) /* Bus Busy Flag */

/* UCBxTBCNT I2C Control Bits */
#define UCTBCNT7 (0x0080u) /* USCI Byte Counter Bit 7 */
#define UCTBCNT6 (0x0040u) /* USCI Byte Counter Bit 6 */
#define UCTBCNT5 (0x0020u) /* USCI Byte Counter Bit 5 */
#define UCTBCNT4 (0x0010u) /* USCI Byte Counter Bit 4 */
#define UCTBCNT3 (0x0008u) /* USCI Byte Counter Bit 3 */
#define UCTBCNT2 (0x0004u) /* USCI Byte Counter Bit 2 */
#define UCTBCNT1 (0x0002u) /* USCI Byte Counter Bit 1 */
#define UCTBCNT0 (0x0001u) /* USCI Byte Counter Bit 0 */

/* UCAxIRCTL Control Bits */
#define UCIRRXFL5 (0x8000u) /* IRDA Receive Filter Length 5 */
#define UCIRRXFL4 (0x4000u) /* IRDA Receive Filter Length 4 */
#define UCIRRXFL3 (0x2000u) /* IRDA Receive Filter Length 3 */
#define UCIRRXFL2 (0x1000u) /* IRDA Receive Filter Length 2 */
#define UCIRRXFL1 (0x0800u) /* IRDA Receive Filter Length 1 */
#define UCIRRXFL0 (0x0400u) /* IRDA Receive Filter Length 0 */
#define UCIRRXPL (0x0200u) /* IRDA Receive Input Polarity */
#define UCIRRXFE (0x0100u) /* IRDA Receive Filter enable */
#define UCIRTXPL5 (0x0080u) /* IRDA Transmit Pulse Length 5 */
#define UCIRTXPL4 (0x0040u) /* IRDA Transmit Pulse Length 4 */
#define UCIRTXPL3 (0x0020u) /* IRDA Transmit Pulse Length 3 */
#define UCIRTXPL2 (0x0010u) /* IRDA Transmit Pulse Length 2 */
#define UCIRTXPL1 (0x0008u) /* IRDA Transmit Pulse Length 1 */
#define UCIRTXPL0 (0x0004u) /* IRDA Transmit Pulse Length 0 */
#define UCIRTXCLK (0x0002u) /* IRDA Transmit Pulse Clock Select */
#define UCIREN (0x0001u) /* IRDA Encoder/Decoder enable */

/* UCAxIRCTL Control Bits */
#define UCIRTXPL5_L (0x0080u) /* IRDA Transmit Pulse Length 5 */
#define UCIRTXPL4_L (0x0040u) /* IRDA Transmit Pulse Length 4 */
#define UCIRTXPL3_L (0x0020u) /* IRDA Transmit Pulse Length 3 */
#define UCIRTXPL2_L (0x0010u) /* IRDA Transmit Pulse Length 2 */
#define UCIRTXPL1_L (0x0008u) /* IRDA Transmit Pulse Length 1 */
#define UCIRTXPL0_L (0x0004u) /* IRDA Transmit Pulse Length 0 */
#define UCIRTXCLK_L (0x0002u) /* IRDA Transmit Pulse Clock Select */
#define UCIREN_L (0x0001u) /* IRDA Encoder/Decoder enable */

/* UCAxIRCTL Control Bits */
#define UCIRRXFL5_H (0x0080u) /* IRDA Receive Filter Length 5 */
#define UCIRRXFL4_H (0x0040u) /* IRDA Receive Filter Length 4 */
#define UCIRRXFL3_H (0x0020u) /* IRDA Receive Filter Length 3 */
#define UCIRRXFL2_H (0x0010u) /* IRDA Receive Filter Length 2 */
#define UCIRRXFL1_H (0x0008u) /* IRDA Receive Filter Length 1 */
#define UCIRRXFL0_H (0x0004u) /* IRDA Receive Filter Length 0 */
#define UCIRRXPL_H (0x0002u) /* IRDA Receive Input Polarity */
#define UCIRRXFE_H (0x0001u) /* IRDA Receive Filter enable */

/* UCAxABCTL Control Bits */
//#define res (0x80) /* reserved */
//#define res (0x40) /* reserved */
#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
#define UCSTOE (0x08) /* Sync-Field Timeout error */
#define UCBTOE (0x04) /* Break Timeout error */
//#define res (0x02) /* reserved */
#define UCABDEN (0x01) /* Auto Baud Rate detect enable */

/* UCBxI2COA0 Control Bits */
#define UCGCEN (0x8000u) /* I2C General Call enable */
#define UCOAEN (0x0400u) /* I2C Own Address enable */
#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */
#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */
#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */
#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */
#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */
#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */
#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */
#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */
#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */
#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */

/* UCBxI2COA0 Control Bits */
#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */
#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */
#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */
#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */
#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */
#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */
#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */
#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */

/* UCBxI2COA0 Control Bits */
#define UCGCEN_H (0x0080u) /* I2C General Call enable */
#define UCOAEN_H (0x0004u) /* I2C Own Address enable */
#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */
#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */

/* UCBxI2COAx Control Bits */
#define UCOAEN (0x0400u) /* I2C Own Address enable */
#define UCOA9 (0x0200u) /* I2C Own Address Bit 9 */
#define UCOA8 (0x0100u) /* I2C Own Address Bit 8 */
#define UCOA7 (0x0080u) /* I2C Own Address Bit 7 */
#define UCOA6 (0x0040u) /* I2C Own Address Bit 6 */
#define UCOA5 (0x0020u) /* I2C Own Address Bit 5 */
#define UCOA4 (0x0010u) /* I2C Own Address Bit 4 */
#define UCOA3 (0x0008u) /* I2C Own Address Bit 3 */
#define UCOA2 (0x0004u) /* I2C Own Address Bit 2 */
#define UCOA1 (0x0002u) /* I2C Own Address Bit 1 */
#define UCOA0 (0x0001u) /* I2C Own Address Bit 0 */

/* UCBxI2COAx Control Bits */
#define UCOA7_L (0x0080u) /* I2C Own Address Bit 7 */
#define UCOA6_L (0x0040u) /* I2C Own Address Bit 6 */
#define UCOA5_L (0x0020u) /* I2C Own Address Bit 5 */
#define UCOA4_L (0x0010u) /* I2C Own Address Bit 4 */
#define UCOA3_L (0x0008u) /* I2C Own Address Bit 3 */
#define UCOA2_L (0x0004u) /* I2C Own Address Bit 2 */
#define UCOA1_L (0x0002u) /* I2C Own Address Bit 1 */
#define UCOA0_L (0x0001u) /* I2C Own Address Bit 0 */

/* UCBxI2COAx Control Bits */
#define UCOAEN_H (0x0004u) /* I2C Own Address enable */
#define UCOA9_H (0x0002u) /* I2C Own Address Bit 9 */
#define UCOA8_H (0x0001u) /* I2C Own Address Bit 8 */

/* UCBxADDRX Control Bits */
#define UCADDRX9 (0x0200u) /* I2C Receive Address Bit 9 */
#define UCADDRX8 (0x0100u) /* I2C Receive Address Bit 8 */
#define UCADDRX7 (0x0080u) /* I2C Receive Address Bit 7 */
#define UCADDRX6 (0x0040u) /* I2C Receive Address Bit 6 */
#define UCADDRX5 (0x0020u) /* I2C Receive Address Bit 5 */
#define UCADDRX4 (0x0010u) /* I2C Receive Address Bit 4 */
#define UCADDRX3 (0x0008u) /* I2C Receive Address Bit 3 */
#define UCADDRX2 (0x0004u) /* I2C Receive Address Bit 2 */
#define UCADDRX1 (0x0002u) /* I2C Receive Address Bit 1 */
#define UCADDRX0 (0x0001u) /* I2C Receive Address Bit 0 */

/* UCBxADDRX Control Bits */
#define UCADDRX7_L (0x0080u) /* I2C Receive Address Bit 7 */
#define UCADDRX6_L (0x0040u) /* I2C Receive Address Bit 6 */
#define UCADDRX5_L (0x0020u) /* I2C Receive Address Bit 5 */
#define UCADDRX4_L (0x0010u) /* I2C Receive Address Bit 4 */
#define UCADDRX3_L (0x0008u) /* I2C Receive Address Bit 3 */
#define UCADDRX2_L (0x0004u) /* I2C Receive Address Bit 2 */
#define UCADDRX1_L (0x0002u) /* I2C Receive Address Bit 1 */
#define UCADDRX0_L (0x0001u) /* I2C Receive Address Bit 0 */

/* UCBxADDRX Control Bits */
#define UCADDRX9_H (0x0002u) /* I2C Receive Address Bit 9 */
#define UCADDRX8_H (0x0001u) /* I2C Receive Address Bit 8 */

/* UCBxADDMASK Control Bits */
#define UCADDMASK9 (0x0200u) /* I2C Address Mask Bit 9 */
#define UCADDMASK8 (0x0100u) /* I2C Address Mask Bit 8 */
#define UCADDMASK7 (0x0080u) /* I2C Address Mask Bit 7 */
#define UCADDMASK6 (0x0040u) /* I2C Address Mask Bit 6 */
#define UCADDMASK5 (0x0020u) /* I2C Address Mask Bit 5 */
#define UCADDMASK4 (0x0010u) /* I2C Address Mask Bit 4 */
#define UCADDMASK3 (0x0008u) /* I2C Address Mask Bit 3 */
#define UCADDMASK2 (0x0004u) /* I2C Address Mask Bit 2 */
#define UCADDMASK1 (0x0002u) /* I2C Address Mask Bit 1 */
#define UCADDMASK0 (0x0001u) /* I2C Address Mask Bit 0 */

/* UCBxADDMASK Control Bits */
#define UCADDMASK7_L (0x0080u) /* I2C Address Mask Bit 7 */
#define UCADDMASK6_L (0x0040u) /* I2C Address Mask Bit 6 */
#define UCADDMASK5_L (0x0020u) /* I2C Address Mask Bit 5 */
#define UCADDMASK4_L (0x0010u) /* I2C Address Mask Bit 4 */
#define UCADDMASK3_L (0x0008u) /* I2C Address Mask Bit 3 */
#define UCADDMASK2_L (0x0004u) /* I2C Address Mask Bit 2 */
#define UCADDMASK1_L (0x0002u) /* I2C Address Mask Bit 1 */
#define UCADDMASK0_L (0x0001u) /* I2C Address Mask Bit 0 */

/* UCBxADDMASK Control Bits */
#define UCADDMASK9_H (0x0002u) /* I2C Address Mask Bit 9 */
#define UCADDMASK8_H (0x0001u) /* I2C Address Mask Bit 8 */

/* UCBxI2CSA Control Bits */
#define UCSA9 (0x0200u) /* I2C Slave Address Bit 9 */
#define UCSA8 (0x0100u) /* I2C Slave Address Bit 8 */
#define UCSA7 (0x0080u) /* I2C Slave Address Bit 7 */
#define UCSA6 (0x0040u) /* I2C Slave Address Bit 6 */
#define UCSA5 (0x0020u) /* I2C Slave Address Bit 5 */
#define UCSA4 (0x0010u) /* I2C Slave Address Bit 4 */
#define UCSA3 (0x0008u) /* I2C Slave Address Bit 3 */
#define UCSA2 (0x0004u) /* I2C Slave Address Bit 2 */
#define UCSA1 (0x0002u) /* I2C Slave Address Bit 1 */
#define UCSA0 (0x0001u) /* I2C Slave Address Bit 0 */

/* UCBxI2CSA Control Bits */
#define UCSA7_L (0x0080u) /* I2C Slave Address Bit 7 */
#define UCSA6_L (0x0040u) /* I2C Slave Address Bit 6 */
#define UCSA5_L (0x0020u) /* I2C Slave Address Bit 5 */
#define UCSA4_L (0x0010u) /* I2C Slave Address Bit 4 */
#define UCSA3_L (0x0008u) /* I2C Slave Address Bit 3 */
#define UCSA2_L (0x0004u) /* I2C Slave Address Bit 2 */
#define UCSA1_L (0x0002u) /* I2C Slave Address Bit 1 */
#define UCSA0_L (0x0001u) /* I2C Slave Address Bit 0 */

/* UCBxI2CSA Control Bits */
#define UCSA9_H (0x0002u) /* I2C Slave Address Bit 9 */
#define UCSA8_H (0x0001u) /* I2C Slave Address Bit 8 */

/* UCAxIE UART Control Bits */
#define UCTXCPTIE (0x0008u) /* UART Transmit Complete Interrupt Enable */
#define UCSTTIE (0x0004u) /* UART Start Bit Interrupt Enalble */
#define UCTXIE (0x0002u) /* UART Transmit Interrupt Enable */
#define UCRXIE (0x0001u) /* UART Receive Interrupt Enable */

/* UCAxIE/UCBxIE SPI Control Bits */

/* UCBxIE I2C Control Bits */
#define UCBIT9IE (0x4000u) /* I2C Bit 9 Position Interrupt Enable 3 */
#define UCTXIE3 (0x2000u) /* I2C Transmit Interrupt Enable 3 */
#define UCRXIE3 (0x1000u) /* I2C Receive Interrupt Enable 3 */
#define UCTXIE2 (0x0800u) /* I2C Transmit Interrupt Enable 2 */
#define UCRXIE2 (0x0400u) /* I2C Receive Interrupt Enable 2 */
#define UCTXIE1 (0x0200u) /* I2C Transmit Interrupt Enable 1 */
#define UCRXIE1 (0x0100u) /* I2C Receive Interrupt Enable 1 */
#define UCCLTOIE (0x0080u) /* I2C Clock Low Timeout interrupt enable */
#define UCBCNTIE (0x0040u) /* I2C Automatic stop assertion interrupt enable */
#define UCNACKIE (0x0020u) /* I2C NACK Condition interrupt enable */
#define UCALIE (0x0010u) /* I2C Arbitration Lost interrupt enable */
#define UCSTPIE (0x0008u) /* I2C STOP Condition interrupt enable */
#define UCSTTIE (0x0004u) /* I2C START Condition interrupt enable */
#define UCTXIE0 (0x0002u) /* I2C Transmit Interrupt Enable 0 */
#define UCRXIE0 (0x0001u) /* I2C Receive Interrupt Enable 0 */

/* UCAxIFG UART Control Bits */
#define UCTXCPTIFG (0x0008u) /* UART Transmit Complete Interrupt Flag */
#define UCSTTIFG (0x0004u) /* UART Start Bit Interrupt Flag */
#define UCTXIFG (0x0002u) /* UART Transmit Interrupt Flag */
#define UCRXIFG (0x0001u) /* UART Receive Interrupt Flag */

/* UCAxIFG/UCBxIFG SPI Control Bits */
#define UCTXIFG (0x0002u) /* SPI Transmit Interrupt Flag */
#define UCRXIFG (0x0001u) /* SPI Receive Interrupt Flag */

/* UCBxIFG Control Bits */
#define UCBIT9IFG (0x4000u) /* I2C Bit 9 Possition Interrupt Flag 3 */
#define UCTXIFG3 (0x2000u) /* I2C Transmit Interrupt Flag 3 */
#define UCRXIFG3 (0x1000u) /* I2C Receive Interrupt Flag 3 */
#define UCTXIFG2 (0x0800u) /* I2C Transmit Interrupt Flag 2 */
#define UCRXIFG2 (0x0400u) /* I2C Receive Interrupt Flag 2 */
#define UCTXIFG1 (0x0200u) /* I2C Transmit Interrupt Flag 1 */
#define UCRXIFG1 (0x0100u) /* I2C Receive Interrupt Flag 1 */
#define UCCLTOIFG (0x0080u) /* I2C Clock low Timeout interrupt Flag */
#define UCBCNTIFG (0x0040u) /* I2C Byte counter interrupt flag */
#define UCNACKIFG (0x0020u) /* I2C NACK Condition interrupt Flag */
#define UCALIFG (0x0010u) /* I2C Arbitration Lost interrupt Flag */
#define UCSTPIFG (0x0008u) /* I2C STOP Condition interrupt Flag */
#define UCSTTIFG (0x0004u) /* I2C START Condition interrupt Flag */
#define UCTXIFG0 (0x0002u) /* I2C Transmit Interrupt Flag 0 */
#define UCRXIFG0 (0x0001u) /* I2C Receive Interrupt Flag 0 */

/* USCI UART Definitions */
#define USCI_NONE (0x0000u) /* No Interrupt pending */
#define USCI_UART_UCRXIFG (0x0002u) /* USCI UCRXIFG */
#define USCI_UART_UCTXIFG (0x0004u) /* USCI UCTXIFG */
#define USCI_UART_UCSTTIFG (0x0006u) /* USCI UCSTTIFG */
#define USCI_UART_UCTXCPTIFG (0x0008u) /* USCI UCTXCPTIFG */

/* USCI SPI Definitions */
#define USCI_SPI_UCRXIFG (0x0002u) /* USCI UCRXIFG */
#define USCI_SPI_UCTXIFG (0x0004u) /* USCI UCTXIFG */

/* USCI I2C Definitions */
#define USCI_I2C_UCALIFG (0x0002u) /* USCI I2C Mode: UCALIFG */
#define USCI_I2C_UCNACKIFG (0x0004u) /* USCI I2C Mode: UCNACKIFG */
#define USCI_I2C_UCSTTIFG (0x0006u) /* USCI I2C Mode: UCSTTIFG*/
#define USCI_I2C_UCSTPIFG (0x0008u) /* USCI I2C Mode: UCSTPIFG*/
#define USCI_I2C_UCRXIFG3 (0x000Au) /* USCI I2C Mode: UCRXIFG3 */
#define USCI_I2C_UCTXIFG3 (0x000Cu) /* USCI I2C Mode: UCTXIFG3 */
#define USCI_I2C_UCRXIFG2 (0x000Eu) /* USCI I2C Mode: UCRXIFG2 */
#define USCI_I2C_UCTXIFG2 (0x0010u) /* USCI I2C Mode: UCTXIFG2 */
#define USCI_I2C_UCRXIFG1 (0x0012u) /* USCI I2C Mode: UCRXIFG1 */
#define USCI_I2C_UCTXIFG1 (0x0014u) /* USCI I2C Mode: UCTXIFG1 */
#define USCI_I2C_UCRXIFG0 (0x0016u) /* USCI I2C Mode: UCRXIFG0 */
#define USCI_I2C_UCTXIFG0 (0x0018u) /* USCI I2C Mode: UCTXIFG0 */
#define USCI_I2C_UCBCNTIFG (0x001Au) /* USCI I2C Mode: UCBCNTIFG */
#define USCI_I2C_UCCLTOIFG (0x001Cu) /* USCI I2C Mode: UCCLTOIFG */
#define USCI_I2C_UCBIT9IFG (0x001Eu) /* USCI I2C Mode: UCBIT9IFG */

/************************************************************
* USCI A1
************************************************************/
#define __MSP430_HAS_EUSCI_A1__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_EUSCI_A1__ 0x05E0

#define UCA1CTLW0_ (0x05E0u) /* USCI A1 Control Word Register 0 */
DEFCW( UCA1CTLW0 , UCA1CTLW0_)
#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */
#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */
#define UCA1CTLW1_ (0x05E2u) /* USCI A1 Control Word Register 1 */
DEFCW( UCA1CTLW1 , UCA1CTLW1_)
#define UCA1BRW_ (0x05E6u) /* USCI A1 Baud Word Rate 0 */
DEFCW( UCA1BRW , UCA1BRW_)
#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */
#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */
#define UCA1MCTLW_ (0x05E8u) /* USCI A1 Modulation Control */
DEFCW( UCA1MCTLW , UCA1MCTLW_)
#define UCA1STATW_ (0x05EAu) /* USCI A1 Status Register */
DEFC( UCA1STATW , UCA1STATW_)
#define UCA1RXBUF_ (0x05ECu) /* USCI A1 Receive Buffer */
READ_ONLY_DEFCW( UCA1RXBUF , UCA1RXBUF_)
#define UCA1TXBUF_ (0x05EEu) /* USCI A1 Transmit Buffer */
DEFCW( UCA1TXBUF , UCA1TXBUF_)
#define UCA1ABCTL_ (0x05F0u) /* USCI A1 LIN Control */
DEFC( UCA1ABCTL , UCA1ABCTL_)
#define UCA1IRCTL_ (0x05F2u) /* USCI A1 IrDA Transmit Control */
DEFCW( UCA1IRCTL , UCA1IRCTL_)
#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */
#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */
#define UCA1IE_ (0x05FAu) /* USCI A1 Interrupt Enable Register */
DEFCW( UCA1IE , UCA1IE_)
#define UCA1IFG_ (0x05FCu) /* USCI A1 Interrupt Flags Register */
DEFCW( UCA1IFG , UCA1IFG_)
#define UCA1IV_ (0x05FEu) /* USCI A1 Interrupt Vector Register */
DEFW( UCA1IV , UCA1IV_)


/************************************************************
* USCI A2
************************************************************/
#define __MSP430_HAS_EUSCI_A2__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_EUSCI_A2__ 0x0600

#define UCA2CTLW0_ (0x0600u) /* USCI A2 Control Word Register 0 */
DEFCW( UCA2CTLW0 , UCA2CTLW0_)
#define UCA2CTL1 UCA2CTLW0_L /* USCI A2 Control Register 1 */
#define UCA2CTL0 UCA2CTLW0_H /* USCI A2 Control Register 0 */
#define UCA2CTLW1_ (0x0602u) /* USCI A2 Control Word Register 1 */
DEFCW( UCA2CTLW1 , UCA2CTLW1_)
#define UCA2BRW_ (0x0606u) /* USCI A2 Baud Word Rate 0 */
DEFCW( UCA2BRW , UCA2BRW_)
#define UCA2BR0 UCA2BRW_L /* USCI A2 Baud Rate 0 */
#define UCA2BR1 UCA2BRW_H /* USCI A2 Baud Rate 1 */
#define UCA2MCTLW_ (0x0608u) /* USCI A2 Modulation Control */
DEFCW( UCA2MCTLW , UCA2MCTLW_)
#define UCA2STATW_ (0x060Au) /* USCI A2 Status Register */
DEFC( UCA2STATW , UCA2STATW_)
#define UCA2RXBUF_ (0x060Cu) /* USCI A2 Receive Buffer */
READ_ONLY_DEFCW( UCA2RXBUF , UCA2RXBUF_)
#define UCA2TXBUF_ (0x060Eu) /* USCI A2 Transmit Buffer */
DEFCW( UCA2TXBUF , UCA2TXBUF_)
#define UCA2ABCTL_ (0x0610u) /* USCI A2 LIN Control */
DEFC( UCA2ABCTL , UCA2ABCTL_)
#define UCA2IRCTL_ (0x0612u) /* USCI A2 IrDA Transmit Control */
DEFCW( UCA2IRCTL , UCA2IRCTL_)
#define UCA2IRTCTL UCA2IRCTL_L /* USCI A2 IrDA Transmit Control */
#define UCA2IRRCTL UCA2IRCTL_H /* USCI A2 IrDA Receive Control */
#define UCA2IE_ (0x061Au) /* USCI A2 Interrupt Enable Register */
DEFCW( UCA2IE , UCA2IE_)
#define UCA2IFG_ (0x061Cu) /* USCI A2 Interrupt Flags Register */
DEFCW( UCA2IFG , UCA2IFG_)
#define UCA2IV_ (0x061Eu) /* USCI A2 Interrupt Vector Register */
DEFW( UCA2IV , UCA2IV_)


/************************************************************
* WATCHDOG TIMER A
************************************************************/
#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
#define __MSP430_BASEADDRESS_WDT_A__ 0x0150

#define WDTCTL_ (0x015Cu) /* Watchdog Timer Control */
DEFCW( WDTCTL , WDTCTL_)
/* The bit names have been prefixed with "WDT" */
/* WDTCTL Control Bits */
#define WDTIS0 (0x0001u) /* WDT - Timer Interval Select 0 */
#define WDTIS1 (0x0002u) /* WDT - Timer Interval Select 1 */
#define WDTIS2 (0x0004u) /* WDT - Timer Interval Select 2 */
#define WDTCNTCL (0x0008u) /* WDT - Timer Clear */
#define WDTTMSEL (0x0010u) /* WDT - Timer Mode Select */
#define WDTSSEL0 (0x0020u) /* WDT - Timer Clock Source Select 0 */
#define WDTSSEL1 (0x0040u) /* WDT - Timer Clock Source Select 1 */
#define WDTHOLD (0x0080u) /* WDT - Timer hold */

/* WDTCTL Control Bits */
#define WDTIS0_L (0x0001u) /* WDT - Timer Interval Select 0 */
#define WDTIS1_L (0x0002u) /* WDT - Timer Interval Select 1 */
#define WDTIS2_L (0x0004u) /* WDT - Timer Interval Select 2 */
#define WDTCNTCL_L (0x0008u) /* WDT - Timer Clear */
#define WDTTMSEL_L (0x0010u) /* WDT - Timer Mode Select */
#define WDTSSEL0_L (0x0020u) /* WDT - Timer Clock Source Select 0 */
#define WDTSSEL1_L (0x0040u) /* WDT - Timer Clock Source Select 1 */
#define WDTHOLD_L (0x0080u) /* WDT - Timer hold */

/* WDTCTL Control Bits */

#define WDTPW (0x5A00u)

#define WDTIS_0 (0*0x0001u) /* WDT - Timer Interval Select: /2G */
#define WDTIS_1 (1*0x0001u) /* WDT - Timer Interval Select: /128M */
#define WDTIS_2 (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
#define WDTIS_3 (3*0x0001u) /* WDT - Timer Interval Select: /512k */
#define WDTIS_4 (4*0x0001u) /* WDT - Timer Interval Select: /32k */
#define WDTIS_5 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
#define WDTIS_6 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
#define WDTIS_7 (7*0x0001u) /* WDT - Timer Interval Select: /64 */
#define WDTIS__2G (0*0x0001u) /* WDT - Timer Interval Select: /2G */
#define WDTIS__128M (1*0x0001u) /* WDT - Timer Interval Select: /128M */
#define WDTIS__8192K (2*0x0001u) /* WDT - Timer Interval Select: /8192k */
#define WDTIS__512K (3*0x0001u) /* WDT - Timer Interval Select: /512k */
#define WDTIS__32K (4*0x0001u) /* WDT - Timer Interval Select: /32k */
#define WDTIS__8192 (5*0x0001u) /* WDT - Timer Interval Select: /8192 */
#define WDTIS__512 (6*0x0001u) /* WDT - Timer Interval Select: /512 */
#define WDTIS__64 (7*0x0001u) /* WDT - Timer Interval Select: /64 */

#define WDTSSEL_0 (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
#define WDTSSEL_1 (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
#define WDTSSEL_2 (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */
#define WDTSSEL_3 (3*0x0020u) /* WDT - Timer Clock Source Select: reserved */
#define WDTSSEL__SMCLK (0*0x0020u) /* WDT - Timer Clock Source Select: SMCLK */
#define WDTSSEL__ACLK (1*0x0020u) /* WDT - Timer Clock Source Select: ACLK */
#define WDTSSEL__VLO (2*0x0020u) /* WDT - Timer Clock Source Select: VLO_CLK */

/* WDT-interval times [1ms] coded with Bits 0-2 */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
/* Watchdog mode -> reset after expired time */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */


/************************************************************
* TLV Descriptors
************************************************************/
#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */

#define TLV_START (0x1A08u) /* Start Address of the TLV structure */
#define TLV_END (0x1AFFu) /* End Address of the TLV structure */

#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
#define TLV_Reserved3 (0x03) /* Future usage */
#define TLV_Reserved4 (0x04) /* Future usage */
#define TLV_BLANK (0x05) /* Blank descriptor */
#define TLV_Reserved6 (0x06) /* Future usage */
#define TLV_Reserved7 (0x07) /* Serial Number */
#define TLV_DIERECORD (0x08) /* Die Record */
#define TLV_ADCCAL (0x11) /* ADC12 calibration */
#define TLV_ADC12CAL (0x11) /* ADC12 calibration */
#define TLV_ADC10CAL (0x13) /* ADC10 calibration */
#define TLV_REFCAL (0x12) /* REF calibration */
#define TLV_TAGEXT (0xFE) /* Tag extender */
#define TLV_TAGEND (0xFF) // Tag End of Table

/************************************************************
* Interrupt Vectors (offset from 0xFF80)
************************************************************/


#define RTC_VECTOR (40 * 2u) /* 0xFFD0 RTC */
#define LCD_C_VECTOR (41 * 2u) /* 0xFFD2 LCD C */
#define TIMER3_A1_VECTOR (42 * 2u) /* 0xFFD4 Timer3_A2 CC1, TA */
#define TIMER3_A0_VECTOR (43 * 2u) /* 0xFFD8 Timer3_A2 CC0 */
#define PORT2_VECTOR (44 * 2u) /* 0xFFDA Port 2 */
#define TIMER2_A1_VECTOR (45 * 2u) /* 0xFFDC Timer2_A2 CC1, TA */
#define TIMER2_A0_VECTOR (46 * 2u) /* 0xFFDE Timer2_A2 CC0 */
#define PORT1_VECTOR (47 * 2u) /* 0xFFDE Port 1 */
#define TIMER1_A1_VECTOR (48 * 2u) /* 0xFFE0 Timer1_A2 CC1, TA1 */
#define TIMER1_A0_VECTOR (49 * 2u) /* 0xFFE2 Timer1_A2 CC0 */
#define DMA_VECTOR (50 * 2u) /* 0xFFE4 DMA */
#define AUX_VECTOR (51 * 2u) /* 0xFFE6 AUX Supply */
#define USCI_A2_VECTOR (52 * 2u) /* 0xFFE8 USCI A2 Receive/Transmit */
#define USCI_A1_VECTOR (53 * 2u) /* 0xFFEA USCI A1 Receive/Transmit */
#define TIMER0_A1_VECTOR (54 * 2u) /* 0xFFEC Timer0_A2 CC1-CC2, TA */
#define TIMER0_A0_VECTOR (55 * 2u) /* 0xFFEE Timer0_A2 CC0 */
#define SD24B_VECTOR (56 * 2u) /* 0xFFF0 SD24B ADC */
#define ADC10_VECTOR (57 * 2u) /* 0xFFF2 ADC */
#define USCI_B0_VECTOR (58 * 2u) /* 0xFFF4 USCI B0 Receive/Transmit */
#define USCI_A0_VECTOR (59 * 2u) /* 0xFFF6 USCI A0 Receive/Transmit */
#define WDT_VECTOR (60 * 2u) /* 0xFFF8 Watchdog Timer */
#define UNMI_VECTOR (61 * 2u) /* 0xFFFA User Non-maskable */
#define SYSNMI_VECTOR (62 * 2u) /* 0xFFFC System Non-maskable */
#define RESET_VECTOR (63 * 2u) /* 0xFFFE Reset [Highest Priority] */

/************************************************************
* End of Modules
************************************************************/
#pragma language=default

#endif /* #ifndef __MSP430F6736 */

Thanks Chester Gillon,

Actually i am working on Prepaid meter system ,we have taken Ti solution for this project , the code we got this from TI Pune india , its working in IAR v5.6 platform , but we want to convert it into CCS v6 , i have recently converted Number of IAR code into CCSv6 , the controller is msp430f6736, i am getting issue in #include "msp430F6736_modified.h" file , i have converted other files to ccsv6 ,but unable to do for msp430F6736_modified.h........so please tell me if any thing going wrong with me ,

plse see below some part of #include "msp430F6736_modified.h file


/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for the
* MSP430F6736 device.
*
* Texas Instruments, Version 1.2
*
* Rev. 1.0, Initial Release
* Rev. 1.1, Added missing LCD Registers
* Rev. 1.2, Fixed typo in LCD_C (VLCD) definitions
*
********************************************************************/

#ifndef __MSP430F6736
#define __MSP430F6736

#define __MSP430_HEADER_VERSION__ 1065 /* Beta-Build-Tag: #0023 */

#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#endif

#if (((__TID__ >> 8) & 0x7F) != 0x2b) /* 0x2b = 43 dec */
#error msp430f6736.h file for use with ICC430/A430 only
#endif


#ifdef __IAR_SYSTEMS_ICC__
#include "in430.h"
#pragma language=extended

#define DEFC(name, address) __no_init volatile unsigned char name @ address;
#define DEFW(name, address) __no_init volatile unsigned short name @ address;

#define DEFCW(name, address) __no_init union \
{ \
struct \
{ \
volatile unsigned char name##_L; \
volatile unsigned char name##_H; \
}; \
volatile unsigned short name; \
} @ address;

 Dear Chester Gillon,

Can we remove this file in CCSv6 ,as you said its only for IAR workbench .

Please inform me if any modification required to use it in CCSv6 ,

please reply , i am waiting for your feedback.

Hi Rohit,
For your latest question, you may also want to post your question to the experts in the MSP430 forums

Thanks
ki

rohit warule said:

i am getting issue in #include "msp430F6736_modified.h" file , i have converted other files to ccsv6 ,but unable to do for msp430F6736_modified.h........so please tell me if any thing going wrong with me ,

Have you tried including the msp430f6736.h from CCS, rather than the IAR specific msp430F6736_modified.h file?

Based on the information so far I don't know if this will help, since unsure why a "modified" include file was being used in the project.

If changing from including msp430F6736_modified.h to msp430f6736.h doesn't fix the errors, can you post the complete CCS project which will make it easier to help?