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CCS/DRA746: Possibility of accessing A15 coprocessor from gel files?

Part Number: DRA746
Other Parts Discussed in Thread: SYSBIOS

Tool/software: Code Composer Studio

Have a customer question - Their use case is that they are enabling unaligned access exception in A15 core in bootloader (SCTLR.A bit in MPCore). While connecting to such target from gel files, A15 is reset and SCTLR.A bit is cleared. Is it possible to set it in GEL files again? If yes, can you share some example. If no, maybe it could be done by some sysbios configuration?

  • Hi John,
    Yes it can be set via GEL. The question I have is when and how the customer wants it done. It can be a manual step or automated to occur at a certain point. Do they simply want it to be set once after target connect?

    Thanks
    ki
  • Note that another option is to add it to the customer startup javascript. The can use DSS API to set the register value after the target.connect() call (assuming they want it right after the target connection is complete)
  • Ki,
    Per the customer, they would like to do it just after a15 reset in GEL file. It does not have to be a menu option or any other fancy stuff. Just a simple example of how to access the coprocessor. Please note that this is not a simple register write (it needs to be done using MCR and MRC instructions). If you have some examples of  how to do it in DSS script, please share it (we could use it in the feature).
    John

  • John H. Gardner said:
    Their use case is that they are enabling unaligned access exception in A15 core in bootloader (SCTLR.A bit in MPCore). While connecting to such target from gel files, A15 is reset and SCTLR.A bit is cleared. Is it possible to set it in GEL files again?

    Looking at some GEL files for Cortex-A15 devices in CCS 7.3 shows REG_CTXA15_CP15_C1_SCTLR being used to access the System Control Register. E.g. the AM57xxStartState function <ccs_install_dir>\ccsv7\ccs_base\emulation\boards\am571x\gel\AM570x_startup_common.gel:

    hotmenu AM57xxStartState()
    {
      CPSR &= ~0x20;                 //set to ARM mode
      CPSR = (CPSR & ~0x1F) | 0x13;  //set to privledged mode
      REG_CTXA15_CP15_C1_SCTLR  &= ~0x1; //disable MMU
    }

    I think the following could be added to a GEL file to set the SCTLR.A bit:

      REG_CTXA15_CP15_C1_SCTLR  |= 0x2; // Enable Alignment fault checking