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CCS/AM5728: MCASP DeviceLoopbackExample: GEL error while executing OnTargetConnect

Part Number: AM5728

Tool/software: Code Composer Studio

Hello,

I'm using a Beagleboard x-15 and CCS 8.1. Compiler version GNU v6.3.1 (Linaro). I have imported the MCASP DeviceLoopbackExample from "\ti\pdk_am57xx_1_0_10\packages\MyExampleProjects\MCASP_DeviceLoopback_evmAM572x_armExampleProject" to my workspace and was able to build it. I created a target configuration which looks as follows:

When I launch the targetConfiguration my "NewTargetConfiguration.ccxml"-console prints following error:

Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> AM572x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<---
C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP2: GEL Output: --->>> AM572x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_1: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL: Error while executing OnTargetConnect(): Target failed to read 0x4A0025F4
	 at (*((unsigned int *) 0x4A0025F4)&0xFFF) [AM572x_startup_common.gel:69]
	 at AM57xx_EVM_Initialization(0) [gpevm_am572x.gel:54]
	 at OnTargetConnect()

I am still able to connect to the CortexA15_0 by right click and connect to target. I clicked Run > Load > LoadProgram  and select my .out file. Now I get the following message in my "NewTargetConfiguration.ccxml"-console :

CortexA15_0: GEL Output: --->>> Reset occurs <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---

In the debug view  I can see:

Also an new window shows up:

When I disconnect to CortexA_0 + reconnect and klick "restart" I get following messages:

IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> I2C Init <<<---
CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL already locked, now unlocking....
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Two EMIFs in interleaved mode - (2GB total)
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<----
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

And nothing happens..

I think I made a mistake in my configurations somewhere, but I can't figure out where. Does anyone knows who to solve this issue?

https://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/658821?CCS-AM5728-GEL-error-while-executing-OnTargetConnect says "The GEL file is designed for the AM572x EVM" which I am using, so I assume this can't resolve my problem.

https://e2e.ti.com/support/arm/sitara_arm/f/791/p/558262/2046170#2046170 says that "we recommend you use CCS 6.1.3" which I tried, but ran into other issues. I checked every command that was given as a support and I have all the wished settings. The post ends with the same issue that I have.

Thanks in advance,

Frederic

  • When I click "Debug" I am able to jump into audioSample_main.c main(). When I go step by step trough this:

    for some adresses.After a while I step outside "Board_init()" and go into McASP3_Enable() and got stuck in a while loop in audio_evmInit-c line 157

    	    while (HW_RD_REG32(CSL_DSP_L4PER_CM_CORE_REGS+CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG) != \
    	    		CSL_L4PER_CM_CORE_COMPONENT_CM_L4PER2_MCASP3_CLKCTRL_REG_MODULEMODE_ENABLE) ;

    If I continue debuging and look into Board_uartStdioInit() at evmAM572x_lld_init.c:70 0x8001709c:

    static inline uint32_t HW_RD_REG32_RAW(uint32_t addr)
    {
        uint32_t regVal = *(volatile uint32_t *) addr;
        /* Donot call any functions after this. If required implement as macros */
        HW_SYNC_BARRIER();
        return (regVal);
    }

    I can see following variable assignments:

    which repeats themselves for every Loop. Correct me if I'm wrong, but thats not the assumed result right?

  • Frederic,

    The initial GEL error usually happens if there is code already running on the target - in this case, the x15 board usually requires at least u-boot to be present so the board does not power off after a few seconds. A few additional details are shown at:
    e2e.ti.com/.../2555415

    The message you are getting when stepping through your code is normal and is better explained in the link below:
    software-dl.ti.com/.../sdto_ccs_debug-handbook.html

    Unfortunately I would strongly recommend you to consult with the experts at the Sitara forum for the code execution details of the example project.

    Hope this helps,
    Rafael