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file open issue on ccs5.0

chandrakala madhira
Prodigy 110 points

Hi,

Iam using Beagle board Rev C3 with CCS 5.0 ,CG tools version 4.9.1, compiler TMS470 for cortex A8 device. I have the following code to open a file.

                  fp_r = fopen("abcd.wav","rb");

In my project abcd.wav file does not exist. After this code is executed, Instead of having a NULL pointer in fp_r, fp_r is having an address and junk data is read into the buffer, when attempted to read using this file pointer.

I have tried older CG tools version 4.6.1. problem remains the same, even with older CGtools.

Is this the problem with CCS or am i missing some thing.

Regards,

Chandrakala

 


 

 

  • TI__Guru**** 232700 points

    Start by considering all the issues described on this wiki page.

    Thanks and regards,

    -George

  • in reply to George Mock
    Prodigy 110 points

    Hi George,

    Thanks for the quick reply,

    The code is simple file reading of 512 bytes. The same code works on CCS4.0.2, CGtools 4.6.1. Is this issue with latest CCS version 5.1.0.08012.

    Thanks & Regards,

    Chandrakala.

  • in reply to chandrakala madhira
    TI__Guru**** 232700 points

    Well, let's try to determine whether the compiler or CCS is part of the problem.

    Take the .out file you built with the v4.6.1 compiler.  We know it works under CCS 4.0.2.  That same out file should run just fine under CCS 5.0.  So try that out and let us know what you get.

    You could also do this the other way.  Take the .out file you built with the v4.9.1 compiler.  We know it does not work under CCS 5.0.  See if works under CCS 4.0.2.  Please try this out and let us know what you see.

    Thanks and regards,

    -George

  • in reply to George Mock
    Prodigy 110 points

    Thanks George for the reply.

    we tried testing .out generated by CCS 4.0.2. with CG tools 4.6.1 on CCS5.0. CCS5.0 is not able to open the input file .

    CCS 4.0.2 with CGtools 4.9.1 is  working fine. 

    iam using  XDS100V2 USB emulator and CCS5.0  on windows XP machine.  Is this the problem with emulator or do i need to install any kind of extra drivers.

    Regards,

    Chandrakala

     

  • in reply to chandrakala madhira
    TI__Guru**** 168357 points

    Chandrakala,

    I did some testing here in my system and managed to reproduce the same issues as you reported in CCSv4.2.4, CCSv5.0.x and even 5.1.x (I don't have 4.0.2 as it is rather old).

    However, since I am running Windows 7 I noticed that this issue only occurs if I attempt to write to specific areas that are protected by the UAC (I was originally trying to write to C:\). The moment I redirected the file location to an unprotected area (I used C:\TMP) the code started working fine (check the screen below with the console output in CCSv5.1).

    Check the testcase attached created with CCSv4.2.4 (can be imported to CCSv5). My debug platform is a Beagleboard C1 with a XDS100v2.

    Hope this helps,

    Rafael

    CIO_test_CortexA.zip
  • in reply to desouza
    Prodigy 110 points

    2072.Init.txt 
    ;==================================================================
; Copyright ARM Ltd 2005. All rights reserved.
;
; Cortex-A8 Dhrystone example - Startup Code
;==================================================================

        ;PRESERVE8
        ;AREA   CORTEXA8, CODE, READONLY

        ;ENTRY

; Standard definitions of mode bits and interrupt (I & F) flags in PSRs
	.global Start
	.IMPORT  _c_int00                      ; before MMU enabled import label to __main

Mode_USR        .EQU     0x10
Mode_FIQ        .EQU     0x11
Mode_IRQ        .EQU     0x12
Mode_SVC        .EQU     0x13
Mode_ABT        .EQU     0x17
Mode_UNDEF      .EQU     0x1B
Mode_SYS        .EQU     0x1F

I_Bit           .EQU     0x80 ; when I bit is set, IRQ is disabled
F_Bit           .EQU     0x40 ; when F bit is set, FIQ is disabled

St_Base			.EQU	 0x80000000
TTB_Base		.EQU	 0x80008000

St_Base_new: .word St_Base
TTB_Base_new: .word TTB_Base

_c_int00_new: .word _c_int00

;==================================================================
; Disable Cortex-A8 MMU if enabled 
;==================================================================

Start

        MRC     p15, #0, r0, c1, c0, #0       ; Read CP15 Control Register into r0
        TST     r0, #0x1                    ; Is the MMU enabled?
        BICNE   r0, r0, #0x1                ; Clear bit 0
        MCRNE   p15, #0, r0, c1, c0, #0       ; Write value back
        
;==================================================================
; Initialise Supervisor Mode Stack
; Note stack must be 8 byte aligned.
;==================================================================


        ;.IMPORT  ||Image$$STACK$$ZI$$Limit|| ; Linker symbol from scatter file
        ;LDR     SP, =||Image$$STACK$$ZI$$Limit||
        LDR		 SP, St_Base_new
        ;LDR SP,c_stack
    
;==================================================================
; TLB maintenance, Invalidate Data and Instruction TLB's
;==================================================================
        
        MOV    r0,#0
        MCR    p15, #0, r0, c8, c7, #0 ; Cortex-A8 I-TLB and D-TLB invalidation
        
;==================================================================
; Cache Invalidation code for Cortex-A8
;==================================================================     
        
        ; Invalidate L1 Instruction Cache
        
        MRC p15, #1, r0, c0, c0, #1   ; Read CLIDR
        TST r0, #0x3                ; Harvard Cache?
        MOV r0, #0
        MCRNE p15, #0, r0, c7, c5, #0 ; Invalidate Instruction Cache
        
        ; Invalidate Data/Unified Caches
        
        MRC p15, #1, r0, c0, c0, #1   ; Read CLIDR
        ANDS r3, r0, #0x7000000
        MOV r3, r3, LSR #23         ; Total cache levels << 1
        BEQ Finished
    
        MOV r10, #0                 ; R10 holds current cache level << 1
Loop1   ADD r2, r10, r10, LSR #1    ; R2 holds cache "Set" position 
        MOV r1, r0, LSR r2          ; Bottom 3 bits are the Cache-type for this level
        AND r1, R1, #7              ; Get those 3 bits alone
        CMP r1, #2
        BLT Skip                    ; No cache or only instruction cache at this level
        
        MCR p15, #2, r10, c0, c0, #0  ; Write the Cache Size selection register
        MOV r1, #0
        MCR p15, #0, r1, c7, c5, #4   ; PrefetchFlush to sync the change to the CacheSizeID reg
        MRC p15, #1, r1, c0, c0, #0   ; Reads current Cache Size ID register
        AND r2, r1, #0x7             ; Extract the line length field
        ADD r2, r2, #4              ; Add 4 for the line length offset (log2 16 bytes)
        ;LDR r4, =0x3FF
        MOV	r4,#0x03FF
        MOVT r4,#0x0000
        ANDS r4, r4, r1, LSR #3     ; R4 is the max number on the way size (right aligned)
        CLZ r5, r4                  ; R5 is the bit position of the way size increment
        ;LDR r7, =0x00007FFF
        MOV	r7,#0x7fff
        MOVT r7,#0x0000
        ANDS r7, r7, r1, LSR #13    ; R7 is the max number of the index size (right aligned)

Loop2   MOV r9, r4                  ; R9 working copy of the max way size (right aligned)

Loop3   ORR r11, r10, r9, LSL r5    ; Factor in the Way number and cache number into R11
        ORR r11, r11, r7, LSL r2    ; Factor in the Set number
        ;MCR p15, #0, r11, c7, c10, #2 ; Clean by set/way
        MCR p15, #0, r11, c7, c6, #2 ; Clean by set/way
        SUBS r9, r9, #1             ; Decrement the Way number
        BGE Loop3
        SUBS r7, r7, #1             ; Decrement the Set number
        BGE Loop2
Skip    ADD r10, r10, #2            ; increment the cache number
        CMP r3, r10
        BGT Loop1
        
Finished
            
        mcr	p15, #0, r10, c7, c5, #4		; flush prefetch buffer,
										;with armv7 this is 'isb',
										; but we compile with armv5
;===================================================================
; Cortex-A8 MMU Configuration
; Set translation table base
;===================================================================


        .IMPORT ||Image$$TTB$$ZI$$Base||  ; from scatter file.;
    
        ; Cortex-A8 supports two translation tables
        ; Configure translation table base (TTB) control register cp15,c2
        ; to a value of all zeros, indicates we are using TTB register 0.
 
        MOV     r0,#0x0
        MCR     p15, #0, r0, c2, c0, #2
        
        ; write the address of our page table base to TTB register 0.;
        ; We are setting to outer-noncachable [4:3] is zero
 
        ;LDR     r0,=||Image$$TTB$$ZI$$Base||
        ;MOV		r0, TTB_Base_new
        LDR		r0, TTB_Base_new
        MCR     p15, #0, r0, c2, c0, #0              
            
                
;===================================================================
; Cortex-A8 PAGE TABLE generation, using standard Arch v6 tables 
;
; AP[11:10]   - Access Permissions = b11, Read/Write Access
; Domain[8:5] - Domain = b1111, Domain 15
; Type[1:0]   - Descriptor Type = b10, 1Mb descriptors
;
; TEX  C  B 
; 000  0  0  Strongly Ordered 
; 001  1  1  Outer and inner write back, write allocate Normal
;===================================================================

        ;LDR     r1,=0xfff                   ; loop counter
        MOV		r1,#0x0fff
        MOVT	r1,#0x0000
        ;LDR     r2,=2_00000000000000000000110111100010
        MOV		r2,#0x0DE2
        MOVT	r2,#0x0000
        ; r0 contains the address of the translation table base
        ; r1 is loop counter
        ; r2 is level1 descriptor (bits 19:0)

        ; use loop counter to create 4096 individual table entries
        ; this writes from address 0x7FFC down to 0x4000 in word steps (4bytes).

init_ttb_1

        ORR     r3, r2, r1, LSL#20          ; r3 now contains full level1 descriptor to write

		MOV		r4,#0x0
        cmp 	r3,#0x40000000
        BLE		next
        cmp 	r3,#0x50000000
        MOVLE	r4,#0x1
        
next:   cmp		r4,#0x1
        ORRNE		r3,r3,#0xc                  ; This is used to set the CB bits for Normal mode  
        ORRNE		r3,r3,#0x1000               ; Added to test 
        
        STR     r3, [r0, r1, LSL#2]         ; str table entry at TTB base + loopcount*4
        SUBS    r1, r1, #1                  ; decrement loop counter
        BPL     init_ttb_1

        ; In this example we will change the cacheable attribute in the first descriptor.
        ; Virtual memory from 0 to 1MB will be cacheable (write back mode).
        ; TEX[14:12]=001 and CB[3:2]= 11, Outer and inner write back, write allocate.

        ;ORR     r3,r3,#2_0000000001100      ; Set CB bits
        ORR		r3,r3,#0xc 
        ;ORR     r3,r3,#2_1000000000000      ; Set TEX bits
        ORR		r3,r3,#0x1000
        STR     r3,[r0]
        
        MOV		r1,#0x0fff
        MOVT	r1,#0x0000
        ;LDR     r2,=2_00000000000000000000110111100010
        MOV		r2,#0x0DE2
        MOVT	r2,#0x0000
        
;===================================================================        
; Setup domain control register - Enable all domains to client mode
;===================================================================

        MRC     p15, #0, r0, c3, c0, #0     ; Read Domain Access Control Register
        ;LDR     r0, =0x55555555           ; Initialize every domain entry to b01 (client)
        MOV		r0, #0x5555
        MOVT	r0, #0x5555
        MCR     p15, #0, r0, c3, c0, #0     ; Write Domain Access Control Register          
                
;===================================================================
; Setup L2 Cache - L2 Cache Auxiliary Control   
;===================================================================    

		MRC     p15, #1, r0, c9, c0, #2      ; Read L2 Auxilary Control Register
        MOV     r0, #0         
        ;MCR     p15, #1, r0, c9, c0, #2      ; Write L2 Auxilary Control Register 
    
;==================================================================
; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
; Enables Full Access i.e. in both priv and non priv modes
;==================================================================
    
        MRC     p15, #0, r0, c1, c0, #2      ; read CP access register
        ORR     r0, r0, #(0x3  <<20)       ; enable access CP 10
        ORR     r0, r0, #(0x3  <<22)       ; enable access CP 11        
        MCR     p15, #0, r0, c1, c0, #2      ; write CP access register back  
        
;==================================================================
; Switch on the VFP and Neon Hardware
;=================================================================
    
        MOV     r0, #0                      ; Set up a register
        ORR     r0, r0, #(0x1 << 30)        
        FMXR    FPEXC, r0                   ; Write FPEXC register, EN bit set.                
                
;===================================================================
; Enable MMU and Branch to __main
;===================================================================

        ;.IMPORT  _c_int00                      ; before MMU enabled import label to __main
        LDR     r12,_c_int00_new                 ; save this in register for possible long jump


        MRC     p15, #0, r0, c1, c0, #0       ; read CP15 register 1 into r0
        ORR     r0, r0, #0x1                ; enable MMU before scatter loading
        MCR     p15, #0, r0, c1, c0, #0       ; write CP15 register 1


; Now the MMU is enabled, virtual to physical address translations will occur. 
; This will affect the next instruction fetches.
;
; The two instructions currently in the ARM pipeline will have been fetched 
; before the MMU was enabled. This property is useful because the next two 
; instructions are safe even if new instruction fetches fail. If this routine
; was mapped out of the new virtual memory map, the branch to __main would 
; still succeed.

        BX      r12                         ; branch to __main  C library entry point

        .END                                 ; mark the end of this file

     

    5314.boot.txt 
    ;******************************************************************************
;* BOOT  v4.6.1                                                               *
;* Copyright (c) 1996-2009 Texas Instruments Incorporated                     *
;******************************************************************************

;****************************************************************************
;* BOOT.ASM
;*
;* THIS IS THE INITAL BOOT ROUTINE FOR TMS470 C++ PROGRAMS.
;* IT MUST BE LINKED AND LOADED WITH ALL C++ PROGRAMS.
;* 
;* THIS MODULE PERFORMS THE FOLLOWING ACTIONS:
;*   1) ALLOCATES THE STACK AND INITIALIZES THE STACK POINTER
;*   2) CALLS AUTO-INITIALIZATION ROUTINE
;*   3) CALLS THE FUNCTION MAIN TO START THE C++ PROGRAM
;*   4) CALLS THE STANDARD EXIT ROUTINE
;*
;* THIS MODULE DEFINES THE FOLLOWING GLOBAL SYMBOLS:
;*   1) __stack     STACK MEMORY AREA
;*   2) _c_int00    BOOT ROUTINE
;*
;****************************************************************************
   .if  __TI_TMS470_V7M3__
	.thumbfunc _c_int00
   .else
	.armfunc _c_int00
   .endif

;****************************************************************************
; Accomodate different lowerd names in different ABIs
;****************************************************************************
   .if   __TI_EABI_ASSEMBLER
        .asg	_args_main,   ARGS_MAIN_RTN
        .asg	exit,         EXIT_RTN
        .asg    main_func_sp, MAIN_FUNC_SP
   .elseif __TI_ARM9ABI_ASSEMBLER | .TMS470_32BIS
        .asg	__args_main,   ARGS_MAIN_RTN
        .asg	_exit,         EXIT_RTN
        .asg    _main_func_sp, MAIN_FUNC_SP
   .else
        .asg	$_args_main,   ARGS_MAIN_RTN
        .asg	$exit,         EXIT_RTN
        .asg    _main_func_sp, MAIN_FUNC_SP
   .endif

   .if .TMS470_16BIS

;****************************************************************************
;*  16 BIT STATE BOOT ROUTINE                                               *
;****************************************************************************

   .if __TI_TMS470_V7M3__
	.state16
   .else
	.state32
   .endif

	.global	__stack
;***************************************************************
;* DEFINE THE USER MODE STACK (DEFAULT SIZE IS 512)               
;***************************************************************
__stack:.usect	".stack", 0, 4

	.global	_c_int00

;***************************************************************
;* FUNCTION DEF: _c_int00                                      
;***************************************************************
_c_int00: .asmfunc

	.if !__TI_TMS470_V7M3__
	
	;==================================================================
; Global Enable for Cortex-A8 Instruction and Data Caching
;==================================================================

        MRC     p15, #0, r0, c1, c0, #0       ; read CP15 register 1 into r0
        ORR     r0, r0, #(0x1  <<12)        ; enable I Cache
        ORR     r0, r0, #(0x1  <<2)         ; enable D Cache
        MCR     p15, #0, r0, c1, c0, #0       ; write CP15 register 1

;==================================================================
; Enable Cortex-A8 Level2 Unified Cache
;==================================================================

        MRC p15, #0, r0, c1, c0, #1           ; Read Auxiliary Control Register
        ORR r0, r0, #2                          ; L2EN bit, disable L2 cache
        MCR p15, #0, r0, c1, c0, #1           ; Write Auxiliary Control Register

;==================================================================
; Cortex-A8 program flow prediction
;==================================================================

        MRC     p15, #0, r0, c1, c0, #0       ; read CP15 register 1 into r0
        ORR     r0, r0, #(0x1  <<11)        ; Enable all forms of branch prediction
        MCR     p15, #0, r0, c1, c0, #0       ; write CP15 register 1

;==================================================================
	;------------------------------------------------------
	;* SET TO USER MODE
        ;*------------------------------------------------------
        ;MRS     r0, cpsr
        ;BIC     r0, r0, #0x1F  ; CLEAR MODES
        ;ORR     r0, r0, #0x10  ; SET USER MODE
        ;MSR     cpsr_cf, r0

        ;*------------------------------------------------------
	;* CHANGE TO 16 BIT STATE
        ;*------------------------------------------------------
	ADD	r0, pc, #1
	BX	r0

	.state16
	.endif

	;*------------------------------------------------------
        ;* INITIALIZE THE USER MODE STACK                      
        ;*------------------------------------------------------
	LDR     r0, c_stack
	MOV	sp, r0
        LDR     r0, c_STACK_SIZE
	ADD	sp, r0

	;*-----------------------------------------------------
	;* ALIGN THE STACK TO 64-BITS IF EABI.
	;*-----------------------------------------------------
	.if __TI_EABI_ASSEMBLER
	MOV	r7, sp
	MOV	r0, #0x07
	BIC     r7, r0         ; Clear upper 3 bits for 64-bit alignment.
	MOV	sp, r7
	.endif

	;*-----------------------------------------------------
	;* SAVE CURRENT STACK POINTER FOR SDP ANALYSIS
	;*-----------------------------------------------------
	LDR	r0, c_mf_sp
	MOV	r7, sp
	STR	r7, [r0]

        ;*------------------------------------------------------
        ;* Perform all the required initilizations:
        ;*   - Process BINIT Table
        ;*   - Perform C auto initialization
        ;*   - Call global constructors 
        ;*------------------------------------------------------
        BL      __TI_auto_init

        ;*------------------------------------------------------
	;* CALL APPLICATION                                     
        ;*------------------------------------------------------
        BL      ARGS_MAIN_RTN

        ;*------------------------------------------------------
	;* IF APPLICATION DIDN'T CALL EXIT, CALL EXIT(1)
        ;*------------------------------------------------------
        MOV     r0, #1
        BL      EXIT_RTN

        ;*------------------------------------------------------
	;* DONE, LOOP FOREVER
        ;*------------------------------------------------------
L1:     B	L1
	.endasmfunc

   .else           ; !.TMS470_16BIS

;****************************************************************************
;*  32 BIT STATE BOOT ROUTINE                                               *
;****************************************************************************

	.global	__stack
;***************************************************************
;* DEFINE THE USER MODE STACK (DEFAULT SIZE IS 512)            
;***************************************************************
__stack:.usect	".stack", 0, 4

	.global	_c_int00
;***************************************************************
;* FUNCTION DEF: _c_int00                                      
;***************************************************************
_c_int00: .asmfunc

	;==================================================================
; Global Enable for Cortex-A8 Instruction and Data Caching
;==================================================================

        MRC     p15, #0, r0, c1, c0, #0       ; read CP15 register 1 into r0
        ORR     r0, r0, #(0x1  <<12)        ; enable I Cache
        ORR     r0, r0, #(0x1  <<2)         ; enable D Cache
        MCR     p15, #0, r0, c1, c0, #0       ; write CP15 register 1

;==================================================================
; Enable Cortex-A8 Level2 Unified Cache
;==================================================================

        MRC p15, #0, r0, c1, c0, #1           ; Read Auxiliary Control Register
        ORR r0, r0, #2                          ; L2EN bit, disable L2 cache
        MCR p15, #0, r0, c1, c0, #1           ; Write Auxiliary Control Register

;==================================================================
; Cortex-A8 program flow prediction
;==================================================================

        MRC     p15, #0, r0, c1, c0, #0       ; read CP15 register 1 into r0
        ORR     r0, r0, #(0x1  <<11)        ; Enable all forms of branch prediction
        MCR     p15, #0, r0, c1, c0, #0       ; write CP15 register 1

;==================================================================
        ;*------------------------------------------------------
	;* SET TO USER MODE
        ;*------------------------------------------------------
        ;MRS     r0, cpsr
        ;BIC     r0, r0, #0x1F  ; CLEAR MODES
        ;ORR     r0, r0, #0x10  ; SET USER MODE
        ;MSR     cpsr_cf, r0

        ;*------------------------------------------------------
        ;* INITIALIZE THE USER MODE STACK                      
        ;*------------------------------------------------------
	LDR     sp, c_stack
        LDR     r0, c_STACK_SIZE
	ADD	sp, sp, r0

	;*-----------------------------------------------------
	;* ALIGN THE STACK TO 64-BITS IF EABI.
	;*-----------------------------------------------------
	.if __TI_EABI_ASSEMBLER
	BIC     sp, sp, #0x07  ; Clear upper 3 bits for 64-bit alignment.
	.endif

	;*-----------------------------------------------------
	;* SAVE CURRENT STACK POINTER FOR SDP ANALYSIS
	;*-----------------------------------------------------
	LDR	r0, c_mf_sp
	STR	sp, [r0]
                
        ;*------------------------------------------------------
        ;* Perform all the required initilizations:
        ;*   - Process BINIT Table
        ;*   - Perform C auto initialization
        ;*   - Call global constructors 
        ;*------------------------------------------------------
        BL      __TI_auto_init

        ;*------------------------------------------------------
	;* CALL APPLICATION                                     
        ;*------------------------------------------------------    
        BL      ARGS_MAIN_RTN

        ;*------------------------------------------------------
	;* IF APPLICATION DIDN'T CALL EXIT, CALL EXIT(1)
        ;*------------------------------------------------------
        MOV     R0, #1
        BL      EXIT_RTN

        ;*------------------------------------------------------
	;* DONE, LOOP FOREVER
        ;*------------------------------------------------------
L1:     B	L1
	.endasmfunc

   .endif    ; !.TMS470_16BIS

;***************************************************************
;* CONSTANTS USED BY THIS MODULE
;***************************************************************
c_stack		.long    __stack
c_STACK_SIZE  	.long    __STACK_SIZE
c_mf_sp	        .long    MAIN_FUNC_SP

	.if __TI_EABI_ASSEMBLER
        .data
        .align 4
_stkchk_called:
        .field          0,32
        .else
        .sect   ".cinit"
        .align  4
        .field          4,32
        .field          _stkchk_called+0,32
        .field          0,32

        .bss    _stkchk_called,4,4
        .symdepend ".cinit", ".bss"
        .symdepend ".cinit", ".text"
        .symdepend ".bss", ".text"
	.endif

;******************************************************
;* UNDEFINED REFERENCES                               *
;******************************************************
	.global _stkchk_called
	.global	__STACK_SIZE
	.global ARGS_MAIN_RTN
	.global MAIN_FUNC_SP
	.global	EXIT_RTN
        .global __TI_auto_init

	.end

    Thanks Rafael.

    we found that the issue is not with the access to restricted area. It is because of using boot code. please find the attached files. in Init.txt we have enabled MMU. boot.txt deals with stack initializations. if we remove these 2 files from the project, file reads are working fine. when these 2 files are added, file reads are not happening. The reason for adding these 2 files to the project, is to support MMU and VFPV3. Is there any problem in these 2 files.

    these 2 files are used for CCS4.0.2 CGtools 4.6.1. there was no file read issue observed. Issue is observed with CCS5.0. CGtools 4.9.1and CGtools4.6.1.  Is this problem is with CCS or the boot files.

    Regards,

    Chandrakala

     

  • in reply to chandrakala madhira
    TI__Guru**** 232700 points

    I recognize the boot.txt file.  It is the boot routine supplied with the TI ARM compiler, though it has been modified.  I've never seen the init.txt file before, though it appears to do the same task as boot.txt.  I don't see how your system could use both files.  It must be one or the other.  Who made the changes to boot.txt?  Where does init.txt come from?  It seems you need to talk with whoever supplied you those files to see why they work they way they do.

    Thanks and regards,

    -George

  • in reply to George Mock
    Intellectual 315 points

    Hi Georgem,

    Yes, the boot.txt is the boot routine file supplied with the TI ARM compiler.

    The changes in the boot routine code are:

    Added some code for enabling I cache, D cache, L2 unified cache, branch prediction and removed NEON and VFP enable code.

     

    Init.txt is the file written at our end to enable MMU, enable VFP and NEON before the main  (_c_int00) function starts.

    Init.txt has the code to invalidate I cache, D cache, page table generation, enable MMU bit, enable NEON and  VFP, and then branch to main (_c_int00).

    In Init.txt Start function has the code to enable MMU which will reduce cycles. It is the entry function for the project.

    From this init.txt, after enabling NEON and VFP, MMU it branches to boot routine code (i.e., boot.txt).

     

    By adding these two files in the project, the file open issue occuring. So please suggest me why the problem is occuring by adding them.

     

    Thanks & Regards,

    Vinay

  • in reply to Vinay Kumar37373
    TI__Guru**** 232700 points

    Sorry for the delay ...

    We compiler experts are not familiar with system set up issues such as what happens when you enable the MMU.  So we cannot comment on whether your changes to the system initialization are correct.  I recommend you ask about it on the forum for the processor you are using.  

    Thanks and regards,

    -George