Cortex-LM4F Floating Point Conundrum

Hello Community,

I am stumped with the FPU co-processor on an Cortex-LM4F using CCS v5.2.1.00018.

A brief explanation of my issue:  Enabling or Disabling the FPU through StellarisWare libraries doesn't seem to affect the usage of the FPU.  For example, lab 9 on the TI training videos takes 35000 cycles to generate the 100 point sine function regardless of whether the FPU was enabled or not (power down reset and everything between debugs).  Dissassembly shows all the same instructions.

Either the FPU was never used, or it is enabled elsewhere by the compiler and the FPU enable from the StellarisWare library is pointless.  (Full disclosure, I'm using IQmath for my current application, but this is bugging me and I really want to understand what I'm getting wrong).

Spending ~ 2 days reading through TI & ARM documentation has not shed any light on what's going on.  Using the following, simple demo code:

#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/sysctl.h"
#include "driverlib/fpu.h"
void main(void) {
float num1 = 4.0;
float num2 = 5.0;
float temp1;
float temp2;

//Set clock to 80 MHz
SysCtlClockSet(SYSCTL_SYSDIV_2_5|SYSCTL_USE_PLL|SYSCTL_OSC_MAIN|SYSCTL_XTAL_16MHZ);
 FPULazyStackingEnable();
FPUEnable();
 temp1 = num1 + num2;
temp2 = num1 * num2;
 while(1)
{
}
}

I have looked at the disassembled code and see floating point instructions (great!):

VMOVS           S0, #5.000000e+00

and more oddly, the following instruction which uses the floating point register, but shows up nowhere in any documentation (huh?):

FADDS           S0, S1, S0

In the code above, if I remove the FPU header and comment out the FPUEnable and LazyStacking, the dissassembly is the same.  Can anyone explain to me what's happening, or point to reference material that does?  I'm baffled by the instructions like FADDS, FMUL, etc that look like FP instructions on FP registers, but are supposed to be VADD.32 etc.  Are there compiler options I need to add (like --cpu=Cortex-M4.fp or --fpu=fpv4-sp)?  Does the compiler rename instructions, and if so, is there documentation about it?

Thank you for your help!

2 Replies

  • I'm not an ARM expert, so I can't answer most of your questions, but it seems like you are looking for the option --float_support, which takes one value from the list VFPv2, VFPv3, VFPv3D16, vfplib, fpalib, FPv4SPD16.  I don't know which one is appropriate for your device.  However, since you're already getting VMOVS and FADDS, you are probably already using this option.

    FADDS and VADD.32 are the same instruction.  One or the other of them is the new, UAL syntax.  Where are you seeing FADDS in the disassembly?  Is it in the CCS disassembly window?

    [ Edit: VADD.32 is the newer, preferred UAL syntax -- Archaeologist ]

  • In reply to Archaeologist:

    Hi Archaeologist, thanks for the response.

    Yep, I'm looking in the CCS disassembly window and see the FADDS, FLDS, FSTS, etc, all operating on/with the FPU registers.  I suspected they were FP instructions, but nowhere could I find any documentation on them.  I'll take a look for UAL syntax though and see what that turns up.

    The compiler has the --float_support=FPv4SPD16 flag set, so it seems the FPU is operating.

    Now, I guess I need to look at the StellarisWare FPU library and see if I can figure out why it isn't controlling the FPU.  All the documentation for this part clearly states that the FPU is OFF until enabled.  Does CCS do anything behind the scenes to enable it based on the --float_support flag?

    Again, thanks for your time.