_c_int00 address

what processor?

take a look in the cmd file, there is a line :

.text : {}>> FLASH2 | FLASH /* CODE

it means that the code is writen first in the high part of memory, if you change for:

.text : {}>> FLASH | FLASH2 /* CODE

the code will be writen in the low part of flash mem.

It is pretty likely your linker command file changed a lot.  This wiki article helps you understand linker command files, and thus why the change in linker command files affects things so much.  Theoretically speaking, a change in the location of _c_int00 should not affect anything.  That said, the hardware in your system could be sensitive to this change.  Why do you think the change in where code starts execution makes a difference?

Thanks and regards,

-George

the Processor is: TMS320F2812

I have copied the linker command file I am using with both ccs 3.1 and ccs5 below:

/*
//
//      TMDX BETA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:    blink.cmd
//
// TITLE:    Linker Command File For F2812 eZdsp examples that run out of RAM
//          This linker file assumes the user is booting up in Jump to H0 mode
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.51| 02 Apr 2002 | L.H. | Original Release.
//  0.56| 20 May 2002 | L.H. | No change
//  0.57| 01 Aug 2002 | T.A. | BIOS Memory included, this is additional.
// -----|-------------|------|-----------------------------------------------
//###########################################################################
*/

/* -l biospiecfg.cmd */


SECTIONS
{
   /* .reset indicates the start of _c_int00 for C Code.
   /* When using the boot ROM this section and the CPU vector
   /* table is not needed.  Thus the default type is set to
   /* DESECT */
   .reset              : > VECT1,       PAGE = 0, TYPE = DSECT
   vectors             : > VECT1,       PAGE = 0, TYPE = DSECT
   ramfuncs            : LOAD = FLASH, RUN = RAM_FUNCS, PAGE = 0
   codestart           : > BEGIN,       PAGE = 0
   .mainheader         : > MAIN_HEADER  PAGE = 0

      /* Allocate Peripheral Frame 0 Register Structures:   */
   DevEmuRegsFile    : > DEV_EMU,    PAGE = 1
   FlashRegsFile     : > FLASH_REGS, PAGE = 1
   CsmRegsFile       : > CSM,        PAGE = 1
   CsmPwlFile        : > CSM_PWL,    PAGE = 1
   XintfRegsFile     : > XINTF,      PAGE = 1
   CpuTimer0RegsFile : > CPUTimer0,  PAGE = 1
   CpuTimer1RegsFile : > CPUTimer1,  PAGE = 1
   CpuTimer2RegsFile : > CPUTimer2,  PAGE = 1
   PieCtrlRegsFile   : > PIECTRL,    PAGE = 1
   PieVectTable      : > PIEVECT,    PAGE = 1

       /* Allocate Peripheral Frame 2 Register Structures:   */
   SysCtrlRegsFile   : > SYSTEM28,   PAGE = 1
   GpioMuxRegsFile   : > GPIOMUX,    PAGE = 1
   GpioDataRegsFile  : > GPIODAT,    PAGE = 1
   SciaRegsFile      : > SCI_A,      PAGE = 1
   ScibRegsFile      : > SCI_B,      PAGE = 1
   AdcRegsFile       : > ADC,        PAGE = 1
   EvaRegsFile       : > EV_A,       PAGE = 1
   EvbRegsFile       : > EV_B,       PAGE = 1
   ECanaRegsFile     : > ECAN_A,     PAGE = 1
   ECanaLamsFile     : > ECAN_A_LAMS,PAGE = 1
   ECanaMboxesFile   : > ECAN_A_MBOX,PAGE = 1

       /* Define these areas for assembly alogorithm use.                   */
       /* They are all 64 word blocks that can be accessed in the same page */
   M01               : > M01,        PAGE = 1
   M02               : > M02,        PAGE = 1
   M03               : > M03,        PAGE = 1


   /* Allocate Peripheral Frame 1 Register Structures:   */
   SpiaRegsFile      : > SPI_A,      PAGE = 1
   XIntruptRegsFile  : > XINTRUPT,   PAGE = 1
   SpibRegsFile      : > SPI_B,      PAGE = 1
   McbspaRegsFile    : > MCBSP_A,    PAGE = 1

    /* IQ math sections */
    IQmathTables     : LOAD = BOOTROM, type = NOLOAD, PAGE = 0
    IQmath           : > FLASH, PAGE = 0

}