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Accurate MSP430 function max instruction cycle prediction?

Hi,

MSP430 CPUs are used without external memory, both instruction and data are contained in internal RAM/flash, and there is usually no data/instruction cache nor multicore pipeline/optimization.

If our purpose is to guarantee real-time response for some function, then is there a way to calculate maximum cycles for the function to return?

We generally assume no other interrupts will be invoked during call of the function, and the control flow of the function is well-defined and code is well written (no syntax error, size overflow, incorrect address access, etc.).

The function’s internal might have if/else/switch/while, which translates to JMP etc. instructions. We make sure no bugs like infinite loop, etc. exist.

Using TI tools like cg_xml, we can calculate max stack depth for each function; Similarly, is there a way to get the maximum instructions needed for the function? For example, can the compiler calculate linear (count instruction) length of each switch branches, they use the max of all branches as the max instruction cycle length, at least for the switch statement?

 

This should be basic problems for real-time system design and TI should have extensive experience with it. Please advise us of any tools/solutions available.

 

 

John

  • The compiler tools don't provide function execution time estimates for the simple reason that it's a very difficult problem in general. For a loop that executes a fixed number of iterations, it's not too bad, but how about a loop that traverses a linked list? Also, the compiler could not in general ignore the effects of memory delays. You'll probably have more success asking in the MSP-specific forum.