Hello,
I'd like to have the compiler issue a STDW instruction when accessing 64-bit. The compiler issues two STW instructions now. I'm concerned if an interrupt is occurred between two instructions. The interrupt refers to a destination memory stored STW. I think the interrupt refers to only 32-bit data which is stored by 1st STW.
This is my compiler information.
CCSv5.5
CGTv7.3.23
-mv6740 -O3 --include_path="C:/ti/c6000_7.3.23/include" --display_error_number --diag_warning=225 --abi=coffabi --opt_for_speed=5 -k
This is sample code.
volatile long long data1 = 0x12345678;
volatile long long data2;
volatile long long result;
volatile long long temp;
long long func (void);
int main(void)
{
while (1) {
result = func();
}
}
long long func (void)
{
data2 = data1;
return (data2);
}
interrupt void isr (void)
{
temp = data2;
return;
}
This is assembly code in main function. Each two STW to data2 is consecutive. But depending on program, this pair is separated. So occurring interrupt is easier.
LDW .D2T2 *+DP(_data1),B5 ; |17|
LDW .D2T2 *+DP(_data1+4),B4 ; |17|
NOP 3
STW .D2T2 B5,*+DP(_data2) ; |17|
STW .D2T2 B4,*+DP(_data2+4) ; |17|
LDW .D2T2 *+DP(_data2),B5 ; |18|
BNOP .S1 $C$L1,3 ; |10|
|| LDW .D2T2 *+DP(_data2+4),B4 ; |18|
STW .D2T2 B5,*+DP(_result) ; |11|
STW .D2T2 B4,*+DP(_result+4) ; |11|
; BRANCH OCCURS {$C$L1} ; |10|
Regards,
Kazu
