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msp430-elf-as and repeat

David Schultz
Guru 18875 points
Other Parts Discussed in Thread: MSP430FR5969

GNU as is having trouble with repeat. I am using version 2.24.51.20140505 of the assembler and the target is msp430fr5969.

I tried to use "rpt r15 { rrux.w r6" but the asembler claims that repeat cannot be used with that instruction in spite of it being shown as an example on page 232 of slau367g.

I was able to work around this but I had to hand assemble the code because there is no documented (even the use of rpt isn't documented) way of setting the ZC bit in the extension word. Objdump is completely unaware of the ZC bit because it doesn't show it at all when disassembling this instruction:

    52aa:    cf 19 06 10     rpt r15 { rrcx.w    r6   

Documentation of these features is so limited in slau367 that it is nearly non-existent.

When I brute forced an extension word in front of the rrux.w instruction it ignored the repeat. Which makes me wonder why it was used as an example.

  • 0
    TI__Guru* 84225 points

    Yes, this does seem to be a deficiency in the GNU MSP430 toolchain assembler and disassembler.

    The examples in SLAU367 were developed using the TI MSP430 toolchain, which does accept your example:

     RPT #12 || RRUX.W R6
 RPT R15 || RRUX.W R6
 RPT #12 || RRCX.W R6
 RPT R15 || RRCX.W R6   

    000000: 4B19             RPT #12   RRUX.W  R6
000002: 0610            
000004: CF19             RPT R15   RRUX.W  R6
000006: 0610            
000008: 4B18             RPT #12   RRCX.W  R6
00000a: 0610            
00000c: CF18             RPT R15   RRCX.W  R6
00000e: 0610
  • 0
    TI__Guru**** 232750 points

    Thanks for letting us know about the issue.  I notified the team that develops the MSP430 GCC tools.

    Thanks and regards,

    -George

  • 0 in reply to George Mock
    Guru 18875 points
    Seeing the code generated by another assembler helped a lot as it appears that the problem is that the GNU assembler is using rrum to implement rrux rather than rrc with an extension word. With that additional bit of information in hand I submitted a bug report at bugzilla on as.
  • 0 in reply to David Schultz
    Intellectual 390 points
    Thanks for also filing this bug report with the FSF binutils.

    I have created a patch for the assembler that should fix the problem. You can find the patch here:

    sourceware.org/.../show_bug.cgi

    I would also like to second the point that there is very little documentation from TI (that I could find anyway) about the encoding of synthetic instructions, the RPT pseudo instruction, and how bits in the extension word can be set from assembler sources.

    Cheers
    Nick
  • 0 in reply to Nick Clifton
    Guru 18875 points

    Thanks for killing that bug. I also filed a bug report for the related objdump bug. Fixing that will be required for objdump to correctly display this encoding as rrux rather than rrcx.