Compiler/TMS320F28335: Can the initialization code sequence affect the cpu?

KyungMook Lim93

Prodigy 70 points

Part Number: TMS320F28335

Tool/software: TI C/C++ Compiler

HI.

I'm developing ECU using 28335.

Recently, phenomenon has occurred the ECU died after the code is entered. so i broken four ECUs.....

While searching for the cause, I found that the order of the newly added CAN communication MailBox initialization code was intertwined.

The mailbox initialization code (ID, Direction, etc ...) was declared separately at the bottom of the initialization function instead of the previously set order.

So I modified the initialization code that was declared at the bottom to match the order in which other existing MailBoxes are declared, so the ECU die phenomenon is gone.

Could the initialization code sequence cause a critical problem inside the ECU?

The attached picture is the initialization code of the newly added MailBox and the existing initialization code before the problem was solved.

The problem was solved when I joined the things that were separated from each other like that..

over 7 years ago

0 George Mock over 7 years ago

TI__Guru**** 232640 points

I would like to build this source code down to assembly, then inspect that assembly for possible problems. Please preprocess the file which contains these lines, then attach that to your next post. Show the compiler version. And show all the build options exactly as the compiler sees them.

Thanks and regards,

-George

0 KyungMook Lim93 over 7 years ago in reply to George Mock

Prodigy 70 points

Some variable is modified because declared another header file.

The problematic part of this code is MailBox 0,1

comfiler version is CCS 6.1 & TI v 6.4.2

Thank you

DSP2833x_ECan.c

// TI File $Revision: /main/8 $
// Checkin $Date: June 25, 2008   15:19:07 $
//###########################################################################
//
// FILE:	DSP2833x_ECan.c
//
// TITLE:	DSP2833x Enhanced CAN Initialization & Support Functions.
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################

#include "DSP2833x_Device.h"     // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h"   // DSP2833x Examples Include File

//---------------------------------------------------------------------------
// InitECan:
//---------------------------------------------------------------------------
// This function initializes the eCAN module to a known state.
//
void InitECan(void)
{
   InitECana();
#if DSP28_ECANB
   InitECanb();
#endif // if DSP28_ECANB
}

void InitECana(void)		// Initialize eCAN-A module
{
/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. This is especially true while writing to/reading from a bit
 (or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanaShadow;

	EALLOW;		// EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
									// HECC mode also enables time-stamping feature

	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.SCB = 1;
	ECanaShadow.CANMC.bit.ABO = 1;
	ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//	as a matter of precaution.

	ECanaRegs.CANTA.all	= 0xFFFFFFFF;	/* Clear all TAn bits */

	ECanaRegs.CANRMP.all = 0xFFFFFFFF;	/* Clear all RMPn bits */

	ECanaRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
	ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/
	ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
	{
	    ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );  		// Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
		/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
		   See Note at End of File */
			ECanaShadow.CANBTC.bit.BRPREG = 9;
			//ECanaShadow.CANBTC.bit.BRPREG = 4;
			ECanaShadow.CANBTC.bit.TSEG2REG = 2;
			ECanaShadow.CANBTC.bit.TSEG1REG = 10;
    #endif
	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
	   See Note at End of File */
	    ECanaShadow.CANBTC.bit.BRPREG = 4;
		ECanaShadow.CANBTC.bit.TSEG2REG = 1;
		ECanaShadow.CANBTC.bit.TSEG1REG = 6;
	#endif


    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
	ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaShadow.CANES.all = ECanaRegs.CANES.all;

    do
    {
       ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..

/* Disable all Mailboxes  */
  	ECanaRegs.CANME.all = 0;		// Required before writing the MSGIDs

  	/* Initialization application specific parameters - CCP bootloader */
  	ECanaRegs.CANMD.bit.MD0 = 1;
  	ECanaRegs.CANMD.bit.MD1 = 0;

  	ECanaLAMRegs.LAM0.all = 0UL;

  	ECanaMboxes.MBOX0.MSGID.all = 0x283UL <<18;
  	ECanaMboxes.MBOX1.MSGID.all = 0x284UL <<18;
  	ECanaMboxes.MBOX1.MSGCTRL.all = 8;

  	ECanaRegs.CANME.bit.ME0 = 1;		/* enable mailbox */
  	ECanaRegs.CANME.bit.ME1 = 1;		/* enable mailbox */


// Step last. User specific code:

	ECanaMboxes.MBOX20.MSGID.all = 0;					
	ECanaMboxes.MBOX21.MSGID.all = 0;
	ECanaMboxes.MBOX22.MSGID.all = 0;
	ECanaMboxes.MBOX23.MSGID.all = 0;
	ECanaMboxes.MBOX24.MSGID.all = 0;
	ECanaMboxes.MBOX25.MSGID.all = 0;

	ECanaMboxes.MBOX20.MSGID.bit.STDMSGID = 0x700;		
	ECanaMboxes.MBOX21.MSGID.bit.STDMSGID = 0x710;
	ECanaMboxes.MBOX22.MSGID.bit.STDMSGID = 0x720;
	ECanaMboxes.MBOX23.MSGID.bit.STDMSGID = 0x730;
	ECanaMboxes.MBOX24.MSGID.bit.STDMSGID = 0x740;
	ECanaMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750;

/* Configure Mailbox under test as a Transmit mailbox and Receive mailbox */

    ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
	ECanaShadow.CANMD.bit.MD20 = 1;  // Receive mailbox
	ECanaShadow.CANMD.bit.MD21 = 0;  // Transmit mailbox	
	ECanaShadow.CANMD.bit.MD22 = 0;  // Transmit mailbox
	ECanaShadow.CANMD.bit.MD23 = 0;  // Transmit mailbox
	ECanaShadow.CANMD.bit.MD24 = 0;  // Transmit mailbox
	ECanaShadow.CANMD.bit.MD25 = 0;  // Transmit mailbox	

    ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Enable Mailbox under test */

    ECanaShadow.CANME.all = ECanaRegs.CANME.all;
	ECanaShadow.CANME.bit.ME20 = 1; 	
	ECanaShadow.CANME.bit.ME21 = 1; 	
    ECanaShadow.CANME.bit.ME22 = 1;
	ECanaShadow.CANME.bit.ME23 = 1;
	ECanaShadow.CANME.bit.ME24 = 1; 
	ECanaShadow.CANME.bit.ME25 = 1;	

    ECanaRegs.CANME.all = ECanaShadow.CANME.all;

/* Write to DLC field in Master Control reg */
   
	ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8;	
	ECanaMboxes.MBOX22.MSGCTRL.bit.DLC = 8;
	ECanaMboxes.MBOX23.MSGCTRL.bit.DLC = 8;
	ECanaMboxes.MBOX24.MSGCTRL.bit.DLC = 8;
	ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8;		

    EDIS;
}


#if (DSP28_ECANB)
void InitECanb(void)		// Initialize eCAN-B module
{
/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. This is especially true while writing to/reading from a bit
 (or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanbShadow;

   EALLOW;		// EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

    ECanbShadow.CANTIOC.all = ECanbRegs.CANTIOC.all;
    ECanbShadow.CANTIOC.bit.TXFUNC = 1;
    ECanbRegs.CANTIOC.all = ECanbShadow.CANTIOC.all;

    ECanbShadow.CANRIOC.all = ECanbRegs.CANRIOC.all;
    ECanbShadow.CANRIOC.bit.RXFUNC = 1;
    ECanbRegs.CANRIOC.all = ECanbShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */

	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.SCB = 1;
	ECanbShadow.CANMC.bit.ABO = 1;
	ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

    ECanbMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanbMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//	as a matter of precaution.

	ECanbRegs.CANTA.all	= 0xFFFFFFFF;	/* Clear all TAn bits */

	ECanbRegs.CANRMP.all = 0xFFFFFFFF;	/* Clear all RMPn bits */

	ECanbRegs.CANGIF0.all = 0xFFFFFFFF;	/* Clear all interrupt flag bits */
	ECanbRegs.CANGIF1.all = 0xFFFFFFFF;


/* Configure bit timing parameters for eCANB*/

	ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
	{
	    ECanbShadow.CANES.all = ECanbRegs.CANES.all;
	} while(ECanbShadow.CANES.bit.CCE != 1 ); 		// Wait for CCE bit to be  cleared..


    ECanbShadow.CANBTC.all = 0;

    #if (CPU_FRQ_150MHZ)                       // CPU_FRQ_150MHz is defined in DSP2833x_Examples.h
	/* The following block for all 150 MHz SYSCLKOUT (75 MHz CAN clock) - default. Bit rate = 1 Mbps
	   See Note at end of file */
		ECanbShadow.CANBTC.bit.BRPREG = 9;
		ECanbShadow.CANBTC.bit.TSEG2REG = 2;
		ECanbShadow.CANBTC.bit.TSEG1REG = 10;
	#endif
	#if (CPU_FRQ_100MHZ)                       // CPU_FRQ_100MHz is defined in DSP2833x_Examples.h
	/* The following block is only for 100 MHz SYSCLKOUT (50 MHz CAN clock). Bit rate = 1 Mbps
	   See Note at end of file */
	    ECanbShadow.CANBTC.bit.BRPREG = 4;
		ECanbShadow.CANBTC.bit.TSEG2REG = 1;
		ECanbShadow.CANBTC.bit.TSEG1REG = 6;
	#endif

    ECanbShadow.CANBTC.bit.SAM = 1;
    ECanbRegs.CANBTC.all = ECanbShadow.CANBTC.all;

    ECanbShadow.CANMC.all = ECanbRegs.CANMC.all;
	ECanbShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanbRegs.CANMC.all = ECanbShadow.CANMC.all;

    ECanbShadow.CANES.all = ECanbRegs.CANES.all;

    do
    {
        ECanbShadow.CANES.all = ECanbRegs.CANES.all;
    } while(ECanbShadow.CANES.bit.CCE != 0 ); 		// Wait for CCE bit to be  cleared..


// Disable all Mailboxes
 	ECanbRegs.CANME.all = 0;		// Required before writing the MSGIDs

// Step last. User specific code:

 	ECanbMboxes.MBOX19.MSGID.all = 0;
    ECanbMboxes.MBOX20.MSGID.all = 0;
    ECanbMboxes.MBOX21.MSGID.all = 0;
    ECanbMboxes.MBOX22.MSGID.all = 0;
    ECanbMboxes.MBOX23.MSGID.all = 0;
	ECanbMboxes.MBOX24.MSGID.all = 0;
	ECanbMboxes.MBOX25.MSGID.all = 0;
	ECanbMboxes.MBOX26.MSGID.all = 0;

	ECanbMboxes.MBOX19.MSGID.bit.STDMSGID = 0x701;
    ECanbMboxes.MBOX20.MSGID.bit.STDMSGID = 0x700;
    ECanbMboxes.MBOX21.MSGID.bit.STDMSGID = 0x710;
    ECanbMboxes.MBOX22.MSGID.bit.STDMSGID = 0x720;
    ECanbMboxes.MBOX23.MSGID.bit.STDMSGID = 0x730;
	ECanbMboxes.MBOX24.MSGID.bit.STDMSGID = 0x740;
	ECanbMboxes.MBOX25.MSGID.bit.STDMSGID = 0x750;
	ECanbMboxes.MBOX26.MSGID.bit.STDMSGID = 0x760;

// Configure Mailbox under test as a Transmit mailbox and Receive mailbox

    ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
    ECanbShadow.CANMD.bit.MD19 = 1;  //RX
    ECanbShadow.CANMD.bit.MD20 = 1;  //RX
    ECanbShadow.CANMD.bit.MD21 = 0;  //TX
    ECanbShadow.CANMD.bit.MD22 = 0;  //TX
    ECanbShadow.CANMD.bit.MD23 = 0;  //TX
	ECanbShadow.CANMD.bit.MD24 = 0;  //TX
	ECanbShadow.CANMD.bit.MD25 = 0;  //TX
	ECanbShadow.CANMD.bit.MD26 = 0;  //TX
    ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;

// Enable Mailbox under test 

    ECanbShadow.CANME.all = ECanbRegs.CANME.all;
    ECanbShadow.CANME.bit.ME19 = 1;
    ECanbShadow.CANME.bit.ME20 = 1; // 1 : Mail box Enable, 2 : Mail box Disable.
    ECanbShadow.CANME.bit.ME21 = 1;
    ECanbShadow.CANME.bit.ME22 = 1;
    ECanbShadow.CANME.bit.ME23 = 1;
	ECanbShadow.CANME.bit.ME24 = 1;
	ECanbShadow.CANME.bit.ME25 = 1;
	ECanbShadow.CANME.bit.ME26 = 1;
    ECanbRegs.CANME.all = ECanbShadow.CANME.all;

// Write to DLC field in Master Control reg
    ECanbMboxes.MBOX19.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX20.MSGCTRL.bit.DLC = 8;
	ECanbMboxes.MBOX21.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX22.MSGCTRL.bit.DLC = 8;
	ECanbMboxes.MBOX23.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX24.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8;
    ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8;
/*
// Write to the MSGID field  

   ECanbMboxes.MBOX25.MSGID.all = 0x80000003; // Extended Identifier(Transmit)
   ECanbMboxes.MBOX26.MSGID.all = 0x80000004; // Extended Identifier(Transmit)
   ECanbMboxes.MBOX3.MSGID.all = 0x80000001;  // Extended Identifier(Receive)
   ECanbMboxes.MBOX4.MSGID.all = 0x80000002;  // Extended Identifier(Receive)

// Configure Mailbox under test as a Transmit mailbox and Receive mailbox

   ECanbShadow.CANMD.all = ECanbRegs.CANMD.all;
   ECanbShadow.CANMD.bit.MD25 = 0; //Transmit mailbox
   ECanbShadow.CANMD.bit.MD26 = 0; //Transmit mailbox
   ECanbShadow.CANMD.bit.MD3 = 1;  //Receive mailbox
   ECanbShadow.CANMD.bit.MD4 = 1;  //Receive mailbox
   ECanbRegs.CANMD.all = ECanbShadow.CANMD.all;

// Enable Mailbox under test

   ECanbShadow.CANME.all = ECanbRegs.CANME.all;
   ECanbShadow.CANME.bit.ME25 = 1; // 1 : Mail box Enable, 2 : Mail box Disable.
   ECanbShadow.CANME.bit.ME26 = 1; // 1 : Mail box Enable, 2 : Mail box Disable.
   ECanbShadow.CANME.bit.ME3 = 1;
   ECanbShadow.CANME.bit.ME4 = 1;
   ECanbRegs.CANME.all = ECanbShadow.CANME.all;

// Write to DLC field in Master Control reg
   
   ECanbMboxes.MBOX25.MSGCTRL.bit.DLC = 8;
   ECanbMboxes.MBOX26.MSGCTRL.bit.DLC = 8;
*/
    EDIS;
}
#endif // if DSP28_ECANB


//---------------------------------------------------------------------------
// Example: InitECanGpio:
//---------------------------------------------------------------------------
// This function initializes GPIO pins to function as eCAN pins
//
// Each GPIO pin can be configured as a GPIO pin or up to 3 different
// peripheral functional pins. By default all pins come up as GPIO
// inputs after reset.
//
// Caution:
// Only one GPIO pin should be enabled for CANTXA/B operation.
// Only one GPIO pin shoudl be enabled for CANRXA/B operation.
// Comment out other unwanted lines.


void InitECanGpio(void)
{
   InitECanaGpio();
#if (DSP28_ECANB)
   InitECanbGpio();
#endif // if DSP28_ECANB
}

void InitECanaGpio(void)
{
   EALLOW;

/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

//	GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;	    // Enable pull-up for GPIO30 (CANRXA)
	GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0;	    // Enable pull-up for GPIO18 (CANRXA)

//	GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;	    // Enable pull-up for GPIO31 (CANTXA)
	GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0;	    // Enable pull-up for GPIO19 (CANTXA)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.

//    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
  GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3;   // Asynch qual for GPIO18 (CANRXA)


/* Configure eCAN-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

//	GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;	// Configure GPIO30 for CANRXA operation
  GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3;	// Configure GPIO18 for CANRXA operation
//	GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;	// Configure GPIO31 for CANTXA operation
  GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3;	// Configure GPIO19 for CANTXA operation

    EDIS;
}

#if (DSP28_ECANB)
void InitECanbGpio(void)
{
   EALLOW;

/* Enable internal pull-up for the selected CAN pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

//	GpioCtrlRegs.GPAPUD.bit.GPIO8 = 0;	  // Enable pull-up for GPIO8  (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO12 = 0;   // Enable pull-up for GPIO12 (CANTXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0;   // Enable pull-up for GPIO16 (CANTXB)
  GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;   // Enable pull-up for GPIO20 (CANTXB)

//	GpioCtrlRegs.GPAPUD.bit.GPIO10 = 0;	  // Enable pull-up for GPIO10 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO13 = 0;   // Enable pull-up for GPIO13 (CANRXB)
//  GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0;   // Enable pull-up for GPIO17 (CANRXB)
  GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;   // Enable pull-up for GPIO21 (CANRXB)

/* Set qualification for selected CAN pins to asynch only */
// Inputs are synchronized to SYSCLKOUT by default.
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.

//    GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Asynch qual for GPIO10 (CANRXB)
//  GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Asynch qual for GPIO13 (CANRXB)
//  GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch qual for GPIO17 (CANRXB)
  GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Asynch qual for GPIO21 (CANRXB)

/* Configure eCAN-B pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be eCAN functional pins.

//	GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 2;   // Configure GPIO8 for CANTXB operation
//  GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 2;  // Configure GPIO12 for CANTXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 2;  // Configure GPIO16 for CANTXB operation
  GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3;  // Configure GPIO20 for CANTXB operation

//	GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 2;  // Configure GPIO10 for CANRXB operation
//  GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 2;  // Configure GPIO13 for CANRXB operation
//  GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 2;  // Configure GPIO17 for CANRXB operation
  GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3;  // Configure GPIO21 for CANRXB operation

    EDIS;
}
#endif // if DSP28_ECANB

/*
Note: Bit timing parameters must be chosen based on the network parameters such
as the sampling point desired and the propagation delay of the network.
The propagation delay is a function of length of the cable, delay introduced by
the transceivers and opto/galvanic-isolators (if any).

The parameters used in this file must be changed taking into account the above
mentioned factors in order to arrive at the bit-timing parameters suitable
for a network.

*/

0 George Mock over 7 years ago in reply to KyungMook Lim93

TI__Guru**** 232640 points

Unfortunately, I cannot build the file you sent. It includes header files I do not have. And those header file probably include yet other header files. Preprocessing avoids that problem. Please preprocess the file, and attach that.

And please do not forget to show all the build options exactly as the compiler sees them.

Thanks and regards,

-George

0 KyungMook Lim93 over 7 years ago in reply to George Mock

Prodigy 70 points

Sorry. I attached CCS Project for version 6.1.0

The problem area is notated as " /* Initialization application specific parameter - ProblemArea */ " in 'DSP2833x_ECan.c' source code

In fact, I do not really understand the build options you mentioned, so I attach a lot of pictures.

CAN_TEST.zip

0 George Mock over 7 years ago

TI__Guru**** 232640 points

Thank you for sending in the test case. I thought that perhaps the compiler was changing the order of some of the assignment statements to these mailbox fields. Careful inspection shows that is not the case. I very much doubt the compiler has anything to do with your problem.

KyungMook Lim93 said:
While searching for the cause, I found that the order of the newly added CAN communication MailBox initialization code was intertwined.

I presume you mean the code, as originally written, orders the assignments in a way that is a problem. I lack the expertise to help you with that. I will get the attention of some C2000 software experts.

Thanks and regards,

-George

0 Christopher Chiarella over 7 years ago

TI__Mastermind 30255 points

Hello,

For CAN, you should only use 32-bit accesses to read and write to the registers.
See section 1.3.2.1 in http://www.ti.com/lit/sprueu1

Best Regards
Chris

C2000™︎ microcontrollers

C2000 microcontrollers forum

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