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Compiler/AM3359: CGT PRU 2.1.4 : Document restrictions with MVIx instruction

Part Number: AM3359

Tool/software: TI C/C++ Compiler

Hi,

I could not find anything specific here : http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions or in ccsv6\tools\compiler\ti-cgt-pru_2.1.4\README.txt

3. MVI instruction
MVI is only supported on core revisions 2 and 3. The existing PASM assembler
supports the instruction in a limited form for v1 using pseudo operations.

http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions#Move_Register_File_Indirect_.28MVIx.29  does not talk about any restriction of having the pointer register in r1.bx (x=0..3) but

  MVIB	[*][&][--]REG1[++], [*][&][--]REG2[++]  [, bn]

With clpru assembler, I tried following (PRU core revision = 3 )

    mvib r9.b0, *r1.b0 (compiles)

    mvib r9.b0, *r1.b0 (does not compile - invalid instruction)

    mvib r9.b0, *r0.b0 (does not compile - invalid instruction)

    mvib *r1.b0, r10.b0 (compiles)

However pasm documentation states this - I recommend to clarify this in respective clpru documentation

4.2.3.2 V2 and V3 Core Support
When using the core revision option V2 or V3, most forms of this instruction are available. The following
restrictions apply:
 Register pointer registers are restricted to r1.b0, r1.b1, r1.b2, and r1.b3
 The optional count parameter is not available.