Hi, I noted some problems today when trying to simulate the SN74AS109 flip flop in TINA-TI. Simulations give erroneous results even when the flip flop is used in a simple toggle configuration. Outputs change at both rising and falling edges of the clock and the complement outputs QX_ (X={1,2}) are not the actual complements of their respective QX's (see simulation file in attachement). Furthermore, it seems that even the asynchronous functions CLR_ and PRE_ are not working properly.
Is there any way to resolve this problem or is the simulation model really in fault?
Thank's for your support
Hi Emmanuel,
I think the problem was with the naming of the output nodes using labels. I have modified the circuit. I have used a voltage marker and the circit is giving expected behavior now. Please see attached.
1754.Abnormal SN74AS109 behaviour_fixed.TSC
Best regards,
Nikhil Gupta
Power Modeling Engineer
WEBENCH Design Center
Right, simulation works perfectly now. Sorry for this. Strange however that results are completely erroneous when using standard output labels.