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Import the OPA380 pspice model into ADS

Other Parts Discussed in Thread: OPA380, OPA830

Hello friends,

We bought the OPA380 amplifier, and We want to simulate the whole system before we build it on PCB board, we found the OPA380 Pspice model from http://www.ti.com/product/OPA380, could you tell me how can I import the model into the ADS work space so that I could use the macro model to simulate with some other devices?

  • Hi Xiaoc,

    I am moving your question to the WEBENCH Design team forum who should be able to better assist you.

    I was trying myself to import the Pspice model into ADS but was unsuccessful. Sorry for the delayed response.

    Best Regards,

    Rohit

  • Xiaoc,

    The PSpice model available for the OPA380 is located in the .zip file. You will need the .lib file for the import. If the import gives you any errors or warnings that cannot be resolved, contact the Agilent Technical support. ADS is set up to import PSpice models. There is a You Tube video from EEsof detailing how to do this.

    Britt

  • Xiaoc,

    You can create a model in ADS by importing the macro netlist into an ADS workspace.
    Detailed instructions for importing a netlist into ADS are give at the following URL:
    http://edocs.soco.agilent.com/display/ads201101/Importing+a+netlist+File

    Follow the instructions given at the URL, and use the OPA380.lib as the netlist to be imported.
    When you see the dialog box Netlist Import Options, you should select Pspice as the Input Netlist Dialect.
    The example at the URL uses Hspice, which won't work for the OPA380 Pspice model.

    Please let me know if you have any questions.
    Regards,
    John

  • Hi John, yes I imported the Pspice model of OPA380 into ADS, It doesn't work as expected, while it works well in Pspice and TINA.

  • Hi Britt,

    I imported the Pspice model of OPA380 into ADS without any warnings and errors, but it still doesn't works as expected.

    Xiaoc

  • Xiaoc,

    I am sorry to hear you are having problems.

    Would it be possible to post the converted netlist to this thread?
    If the defaults were used during the netlist import it should be in the ADS workspace home directory and have a .net extension.

    Regards,
    John

  • Hi John, 

    Thanks for reply and help!

    You can find the converted converted netlist in the attachment. Also because of the upload filetype limitation, I change the extension to .txt.

    Thank you again and regards,

    Xiaoc

    6320.opa380.txt
    ; Translated with ADS Netlist Translator (*) 391.shp Jun  5 2013
    ; OPA380
    ;****************************************************************************
    ; (C) Copyright 2011 Texas Instruments Incorporated. All rights reserved.
    ;****************************************************************************
    ;* This model is designed as an aid for customers of Texas Instruments.
    ;* TI and its licensors and suppliers make no warranties, either expressed
    ;* or implied, with respect to this model, including the warranties of
    ;* merchantability or fitness for a particular purpose.  The model is
    ;* provided solely on an "as is" basis.  The entire risk as to its quality
    ;* and performance is with the customer.
    ;***************************************************************************
    ;
    ; This model is subject to change without notice. Texas Instruments
    ; Incorporated is not responsible for updating this model.
    ;
    ;****************************************************************************
    ;
    ;* Released by: Analog eLab Design Center, Texas Instruments Inc.
    ; Part: OPA380
    ; Date: 13JUN2011
    ; Model Type: ALL-IN-ONE
    ; Simulator: PSPICE
    ; Simulator Version: 16.0.0.p001
    ; EVM Order Number: N/A
    ; EVM Users Guide: N/A
    ; Datasheet: SBOS291G - NOVEMBER 2003 - REVISED SEPTEMBER 2007
    ;
    ; Model Version: 1.0
    ;
    ;****************************************************************************
    ;
    ; Updates:
    ;
    ; Version 1.0 :
    ; Release to Web
    ;
    ;****************************************************************************
    ; BEGIN NOTES
    ;
    ; THIS MODEL IS APPLICABLE TO OPA380 & OPA2380
    ; MODEL TEMPERATURE RANGE IS -40 C TO +125 C, NOT ALL PARAMETERS ACCURATELY TRACK THOSE OF AN ACTUAL OPA380
    ; OVER THE FULL TEMPERATURE RANGE BUT ARE AS CLOSE AS PRACTICAL
    ;
    ; CMRR ACCURACY AT DC HAS BEEN TRADED OFF FOR IMPROVED CONVERGENCE -
    ; MODELED CMRR DC IS ONLY 86 DB; ACTUAL OPA380 IS MUCH HIGHER
    ;
    ; END NOTES
    ;
    ; BEGIN FEATURES
    ;
    ; OPEN LOOP GAIN AND PHASE
    ; INPUT OFFSET VOLTAGE
    ; TEMPERATURE EFFECTS SAME
    ; INPUT VOLTAGE NOISE
    ; INPUT CURRENT NOISE
    ; INPUT BIAS CURRENT
    ; TEMPERATURE EFFECTS SAME
    ; INPUT CAPACITANCE
    ; INPUT COMMON MODE VOLTAGE RANGE
    ; INPUT CLAMPS TO RAILS
    ; CMRR WITH FREQUENCY EFFECTS
    ; PSRR WITH FREQUENCY EFFECTS
    ; SLEW RATE
    ; QUIESCENT CURRENT
    ; QUIESCENT CURRENT VS VOLTAGE
    ; RAIL TO RAIL OUTPUT STAGE
    ; HIGH CLOAD EFFECTS
    ; CLASS AB BIAS IN OUTPUT STAGE
    ; OUTPUT CURRENT THROUGH SUPPLIES
    ; OUTPUT CURRENT LIMITING
    ; OUTPUT CLAMPS TO RAILS
    ; OUTPUT SWING VS OUTPUT CURRENT
    ; OUTPUT WILL SWING SLIGHTLY
    ; BELOW -V W EXTERNAL PULLDOWN
    ; TO A SUPPLY MORE NEGATIVE
    ; THAN -V
    ; END FEATURES
    ;
    ; BEGIN MODEL OPA380
    ;
    ; PINOUT ORDER +IN -IN +V -V OUT
    ; PINOUT ORDER  3   2   1  4  6
    define opa380 ( _node3 _node2 _node1 _node4 _node6)
    ;
    R:r81 _node10 _node1 R=1
    R:r82 _node4 _node11 R=1
    R:r84 _node12 _node13 R=700
    R:r85 _node14 _node15 R=1
    R:r86 _node16 _node17 R=1
    dd:d21 _node9 _node1 Mode=1
    dd:d22 _node4 _node9 Mode=1
    din:d23 _node18 0 Mode=1
    din:d24 _node19 0 Mode=1
    I_Source:i24 0 _node18 Idc=0.1e-3
    I_Source:i25 0 _node19 Idc=0.1e-3
    SDD:e25 _node4 0 _node16 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e26 _node1 0 _node15 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:g13 _node18 _node19 _node20 _node21 I[1,0]=0 I[2,0]=5e-6*_v1
    SDD:e28 _node15 0 _node22 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e29 _node16 0 _node23 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e30 _node25 0 _node24 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    R:r88 _node22 _node26 R=1e6
    R:r89 _node23 _node27 R=1e6
    R:r90 _node24 _node28 R=1e6
    R:r91 0 _node26 R=100
    R:r92 0 _node27 R=100
    R:r93 0 _node28 R=100
    SDD:e31 _node28 0 _node29 _node3 I[1,0]=0 F[2,0]=(9.5e-4*_v1)-_v2
    R:r94 _node30 _node25 R=1e3
    R:r95 _node25 _node31 R=1e3
    C:c29 _node22 _node26 C=0.2e-12
    C:c30 _node23 _node27 C=0.2e-12
    C:c31 _node24 _node28 C=6e-9
    SDD:e32 _node27 0 _node32 _node29 I[1,0]=0 F[2,0]=(0.042*_v1)-_v2
    SDD:e33 _node26 0 _node33 _node32 I[1,0]=0 F[2,0]=(0.002*_v1)-_v2
    SDD:e34 _node15 _node16 _node34 _node16 I[1,0]=0 F[2,0]=(0.5*_v1)-_v2
    dd:d27 _node12 _node15 Mode=1
    dd:d28 _node16 _node12 Mode=1
    nout:m24 _node35 _node36 _node11 _node11 Length=3u Width=4000u Mode=1
    pout:m25 _node37 _node38 _node10 _node10 Length=3u Width=4000u Mode=1
    pout:m26 _node39 _node39 _node14 _node14 Length=3u Width=4000u Mode=1
    pin:m27 _node40 _node41 _node42 _node42 Length=3u Width=40u Mode=1
    pin:m28 _node43 _node44 _node42 _node42 Length=3u Width=40u Mode=1
    nout:m29 _node45 _node45 _node17 _node17 Length=3u Width=4000u Mode=1
    R:r96 _node46 _node38 R=100
    R:r97 _node47 _node36 R=100
    SDD:g14 _node48 _node34 _node12 _node34 I[1,0]=0 I[2,0]=0.2e-3*_v1
    R:r98 _node34 _node12 R=100e3
    C:c32 _node13 _node9 C=27e-12
    R:r99 _node16 _node40 R=6e3
    R:r100 _node16 _node43 R=6e3
    C:c33 _node40 _node43 C=3e-12
    C:c34 _node20 0 C=1e-12
    C:c35 _node21 0 C=1e-12
    C:c36 _node9 0 C=1e-12
    V_Source:v27 _node20 _node49 Vdc=-10e-6
    pin:m33 _node50 _node51 _node15 _node15 Length=6u Width=500u Mode=1
    SDD:e35 _node20 0 _node31 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e36 _node21 0 _node30 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    pin:m36 _node51 _node51 _node15 _node15 Length=6u Width=500u Mode=1
    V_Source:v30 _node50 _node42 Vdc=0.8
    R:r105 _node9 _node37 R=40
    R:r106 _node35 _node9 R=22
    jc:j5 _node52 _node20 _node52 Mode=1
    jc:j6 _node52 _node21 _node52 Mode=1
    jc:j7 _node21 _node53 _node21 Mode=1
    jc:j8 _node20 _node53 _node20 Mode=1
    SDD:e38 _node43 _node40 _node54 _node34 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    R:r108 _node54 _node48 R=10e3
    C:c40 _node48 _node34 C=1.5e-12
    SDD:g16 _node12 _node34 _node55 _node34 I[1,0]=0 I[2,0]=-1e-3*_v1
    SDD:g17 _node12 _node34 _node34 _node56 I[1,0]=0 I[2,0]=1e-3*_v1
    SDD:g18 _node45 _node16 _node34 _node57 I[1,0]=0 I[2,0]=1e-3*_v1
    SDD:g19 _node15 _node39 _node58 _node34 I[1,0]=0 I[2,0]=1e-3*_v1
    dd:d31 _node58 _node55 Mode=1
    dd:d32 _node56 _node57 Mode=1
    R:r110 _node55 _node58 R=100e6
    R:r111 _node57 _node56 R=100e6
    R:r112 _node58 _node15 R=1e3
    R:r113 _node16 _node57 R=1e3
    SDD:e39 _node15 _node58 _node15 _node46 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e40 _node57 _node16 _node47 _node16 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    R:r114 _node56 _node34 R=1e6
    R:r115 _node57 _node34 R=1e6
    R:r116 _node34 _node58 R=1e6
    R:r117 _node34 _node55 R=1e6
    C:c46 _node59 _node20 C=0.1e-12
    R:r122 0 _node59 R=220
    SDD:e41 _node18 _node19 _node59 0 I[1,0]=0 F[2,0]=(210*_v1)-_v2
    V_Source:v45 _node15 _node52 Vdc=0.2
    V_Source:v46 _node53 _node16 Vdc=0.2
    SDD:e56 _node60 0 _node20 _node33 I[1,0]=0 F[2,0]=(30e-6*_v1)-_v2
    dd:d51 _node61 0 Mode=1
    R:r139 0 _node60 R=1e9
    R:r140 0 _node61 R=1e9
    V_Source:v55 _node61 _node60 Vdc=0.65
    I_Source:i35 0 _node61 Idc=1e-3
    R:r141 _node49 _node41 R=84e3
    R:r142 _node44 _node21 R=84e3
    C:c49 _node20 _node21 C=1e-12
    qln:q23 _node62 _node63 _node64 Mode=1
    R:r150 _node63 _node65 R=1e3
    R:r151 _node66 _node67 R=1e3
    R:r152 _node68 _node1 R=2
    R:r153 _node4 _node69 R=2
    R:r155 _node70 _node71 R=680
    R:r156 _node72 _node73 R=2
    R:r157 _node64 _node74 R=2
    dd:d54 _node75 _node1 Mode=1
    dd:d55 _node4 _node75 Mode=1
    din:d56 _node76 0 Mode=1
    din:d57 _node77 0 Mode=1
    I_Source:i36 0 _node76 Idc=0.1e-3
    I_Source:i37 0 _node77 Idc=0.1e-3
    SDD:e57 _node4 0 _node64 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e58 _node1 0 _node73 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    dvn:d58 _node78 0 Mode=1
    dvn:d59 _node79 0 Mode=1
    I_Source:i38 0 _node78 Idc=0.1e-3
    I_Source:i39 0 _node79 Idc=0.1e-3
    SDD:e59 _node78 _node79 _node80 _node2 I[1,0]=0 F[2,0]=(0.025*_v1)-_v2
    SDD:g24 _node76 _node77 _node81 _node2 I[1,0]=0 I[2,0]=1.6e-6*_v1
    R:r158 _node4 _node1 R=2e3
    SDD:e60 _node73 0 _node82 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e61 _node64 0 _node83 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e62 _node85 0 _node84 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    R:r160 _node82 _node86 R=1e4
    R:r161 _node83 _node87 R=1e5
    R:r162 _node84 _node88 R=1e5
    R:r163 0 _node86 R=1
    R:r164 0 _node87 R=10
    R:r165 0 _node88 R=10
    SDD:e63 _node88 0 _node89 _node90 I[1,0]=0 F[2,0]=(0.03*_v1)-_v2
    R:r166 _node91 _node85 R=1e3
    R:r167 _node85 _node92 R=1e3
    C:c51 _node82 _node86 C=10e-12
    C:c52 _node83 _node87 C=10e-12
    C:c53 _node84 _node88 C=10e-12
    SDD:e64 _node87 0 _node93 _node89 I[1,0]=0 F[2,0]=(0.3*_v1)-_v2
    SDD:e65 _node86 0 _node81 _node93 I[1,0]=0 F[2,0]=(0.3*_v1)-_v2
    SDD:e66 _node73 _node64 _node94 _node64 I[1,0]=0 F[2,0]=(0.5*_v1)-_v2
    dd:d60 _node70 _node73 Mode=1
    dd:d61 _node64 _node70 Mode=1
    nout:m52 _node95 _node96 _node69 _node69 Length=3u Width=450u Mode=1
    pout:m53 _node97 _node98 _node68 _node68 Length=3u Width=950u Mode=1
    pout:m54 _node99 _node99 _node72 _node72 Length=3u Width=950u Mode=1
    pin:m55 _node100 _node101 _node102 _node102 Length=3u Width=270u Mode=1
    pin:m56 _node103 _node104 _node102 _node102 Length=3u Width=270u Mode=1
    nout:m57 _node105 _node105 _node74 _node74 Length=3u Width=450u Mode=1
    R:r168 _node106 _node98 R=100
    R:r169 _node107 _node96 R=100
    SDD:g25 _node108 _node94 _node70 _node94 I[1,0]=0 I[2,0]=0.2e-3*_v1
    R:r170 _node94 _node70 R=2e6
    C:c54 _node71 _node75 C=1.65e-12
    R:r171 _node64 _node100 R=2e3
    R:r172 _node64 _node103 R=2e3
    C:c55 _node100 _node103 C=0.11e-12
    C:c56 _node81 0 C=3e-12
    C:c57 _node80 0 C=3e-12
    C:c58 _node75 0 C=0.5e-12
    dd:d62 _node96 _node62 Mode=1
    dd:d63 _node109 _node98 Mode=1
    qlp:q24 _node109 _node67 _node73 Mode=1
    V_Source:v58 _node81 _node110 Vdc=0
    pin:m58 _node111 _node112 _node73 _node73 Length=6u Width=500u Mode=1
    SDD:e67 _node81 0 _node92 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e68 _node2 0 _node91 0 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    pin:m59 _node112 _node112 _node73 _node73 Length=6u Width=500u Mode=1
    V_Source:v59 _node111 _node102 Vdc=1
    R:r173 _node113 _node97 R=0.25
    R:r174 _node95 _node75 R=4
    jnc:j11 _node114 _node81 _node114 Mode=1
    jnc:j12 _node114 _node80 _node114 Mode=1
    jnc:j13 _node80 _node115 _node80 Mode=1
    jnc:j14 _node81 _node115 _node81 Mode=1
    C:c59 _node81 _node116 C=1.1e-12
    SDD:e69 _node103 _node100 _node117 _node94 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    R:r175 _node117 _node108 R=1e4
    C:c60 _node108 _node94 C=0.11e-12
    SDD:g26 _node70 _node94 _node118 _node94 I[1,0]=0 I[2,0]=-1e-3*_v1
    SDD:g27 _node70 _node94 _node94 _node119 I[1,0]=0 I[2,0]=1e-3*_v1
    SDD:g28 _node105 _node64 _node94 _node120 I[1,0]=0 I[2,0]=1e-3*_v1
    SDD:g29 _node73 _node99 _node121 _node94 I[1,0]=0 I[2,0]=1e-3*_v1
    dd:d64 _node121 _node118 Mode=1
    dd:d65 _node119 _node120 Mode=1
    R:r176 _node118 _node121 R=100e6
    R:r177 _node120 _node119 R=100e6
    R:r178 _node121 _node73 R=1e3
    R:r179 _node64 _node120 R=1e3
    SDD:e70 _node73 _node121 _node73 _node106 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e71 _node120 _node64 _node107 _node64 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    R:r180 _node119 _node94 R=1e6
    R:r181 _node120 _node94 R=1e6
    R:r182 _node94 _node121 R=1e6
    R:r183 _node94 _node118 R=1e6
    R:r184 _node93 _node81 R=1e9
    R:r185 _node89 _node93 R=1e9
    R:r186 _node90 _node89 R=1e9
    R:r187 _node2 _node80 R=1e9
    R:r188 _node94 _node108 R=1e9
    R:r189 _node106 _node73 R=1e9
    R:r190 _node64 _node107 R=1e9
    R:r191 _node85 0 R=1e9
    I_Source:i41 _node1 _node4 Idc=1.5e-3
    L:l2 _node75 _node6 L=4e-9
    R:r200 _node75 _node6 R=400
    V_Source:v79 _node73 _node114 Vdc=0
    V_Source:v80 _node115 _node64 Vdc=0
    R:r204 _node99 _node73 R=1e8
    R:r205 _node64 _node105 R=1e8
    R:r206 _node69 _node96 R=1e8
    R:r207 _node68 _node98 R=1e8
    R:r209 _node116 _node80 R=100
    R:r226 _node104 _node80 R=400
    R:r227 _node101 _node110 R=400
    SDD:e96 _node1 _node68 _node73 _node66 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    SDD:e97 _node69 _node4 _node65 _node64 I[1,0]=0 F[2,0]=(1*_v1)-_v2
    R:r314 _node112 _node73 R=1e9
    R:r316 _node9 _node122 R=100e3
    C:c69 _node122 _node3 C=75e-12
    C:c70 _node21 _node9 C=67e-12
    R:r318 _node123 _node21 R=900e3
    R:r320 _node2 _node123 R=100e3
    C:c72 _node123 _node6 C=115e-15
    V_Source:v118 _node113 _node75 Vdc=0.4
    R:r325 _node20 _node33 R=1e9
    R:r326 _node32 _node33 R=1e9
    R:r327 _node29 _node32 R=1e9
    R:r328 _node3 _node29 R=1e9
    I_Source:i49 _node99 _node105 Idc=2e-3
    I_Source:i50 _node112 _node64 Idc=360e-6
    I_Source:i51 _node51 _node16 Idc=37.5e-6
    I_Source:i52 _node39 _node45 Idc=20e-6
    C:c74 _node59 _node21 C=0.1e-12
    SDD:g36 _node124 0 _node80 0 I[1,0]=0 I[2,0]=10e-12*_v1
    I_Source:i53 _node80 0 Idc=3e-12
    I_Source:i54 0 _node125 Idc=1e-3
    dd:d67 _node125 0 Mode=1
    V_Source:v120 _node125 _node126 Vdc=0.7
    R:r329 0 _node126 R=1e6
    SDD:e98 _node126 0 _node127 0 I[1,0]=0 F[2,0]=(-571*_v1)-_v2
    R:r330 0 _node127 R=1e6
    R:r331 _node128 _node127 R=1e3
    SDD:g37 _node124 0 _node20 0 I[1,0]=0 I[2,0]=10e-12*_v1
    I_Source:i55 _node20 0 Idc=3e-12
    R:r332 0 _node129 R=1e6
    V_Source:v121 _node130 0 Vdc=73.5
    dd:d68 _node131 _node129 Mode=1
    dd:d69 _node128 _node129 Mode=1
    R:r333 _node131 _node130 R=1e3
    V_Source:v122 _node129 _node132 Vdc=72.8
    R:r334 0 _node132 R=1e6
    SDD:e99 _node132 0 _node124 0 I[1,0]=0 F[2,0]=(1.5*_v1)-_v2
    R:r335 0 _node124 R=1e6
    V_Source:v123 _node90 _node122 Vdc=-15e-3
    R:r338 _node39 _node15 R=1e9
    R:r339 _node16 _node45 R=1e9
    R:r340 _node11 _node36 R=1e9
    R:r341 _node10 _node38 R=1e9
    R:r343 _node51 _node15 R=1e9
    R:r344 _node34 _node9 R=100e3
    R:r345 _node94 _node75 R=50e3
    model dvn Diode Kf=2e-11 Is=1e-16 Ibv=1e-10 Tnom=27 IkModel=1
    model dd Diode Ibv=1e-10 Tnom=27 IkModel=1
    model din Diode Ibv=1e-10 Tnom=27 IkModel=1
    model qln BJT NPN=1 PNP=0 RbModel=1 Tnom=27 Tlev=0 Tlevc=0
    model qlp BJT PNP=1 NPN=0 RbModel=1 Tnom=27 Tlev=0 Tlevc=0
    model jnc JFET NFET=1 PFET=0 Tnom=27
    model jc JFET Is=1e-18 NFET=1 PFET=0 Tnom=27
    model je JFET Is=1e-17 NFET=1 PFET=0 Tnom=27
    model pout MOSFET Kp=200u Vto=-0.7 PMOS=1 NMOS=0 Idsmod=1 Capmod=1 Tnom=27
    model nout MOSFET Kp=200u Vto=0.7 NMOS=1 PMOS=0 Idsmod=1 Capmod=1 Tnom=27
    model pin MOSFET Kp=200u Vto=-0.7 PMOS=1 NMOS=0 Idsmod=1 Capmod=1 Tnom=27
    model nin MOSFET Kp=200u Vto=0.7 NMOS=1 PMOS=0 Idsmod=1 Capmod=1 Tnom=27
    end opa380
    

  • Xiaoc,

    Thank you for uploading the file.

    I was unable to get the OPA380 model to work in the version of ADS I was using: ADS2011.01.

    On the advice of Agilent Customer Support I installed the latest version we have access to, ADS2013.06.

    Using that version, importing the OPA830.lib file gave no errors or warnings, and the macro was used in a ref circuit schematic similar to the one in TINA.
    During a transient sim it does give warnings of a few nodes with no DC path to ground, but the sim completes successfully and gives results very close to the TINA ref circuit.

    The ADS2013.06 workspace with the ref circuit and converted macro is attached to this thread.
    Please give it a try and let me know what you find.
    Please let me know if you have any questions.

    Regards,
    John

    OPA380_ADS2013p06_wrk.zip
  • Hi John, you are right, the result is very close to the datasheet. My previous problem is because of the description of the netlist, the node definition in the netlist is:

    ; PINOUT ORDER +IN -IN +V -V OUT
    ; PINOUT ORDER 3 2 1 4 6
    define opa380 ( _node3 _node2 _node1 _node4 _node6)

    while your test circuit shows that the node should be like:

    ; PINOUT ORDER +IN -IN +V -V OUT
    ; PINOUT ORDER 1 2 3 4 6
    where node 6 equals to node 5 in the Spice model netlist description. So I can not get the right results.

    Thank you soooooooooo much for this, it's very nice of you, and hope you could modify the description of the node in case anyone else's confusing about that.

    Thanks again and have a good weekend!

    Xiaoc