LTSPICE or PSPICE Model for LM56 Dual Output Temperature Switch

Hi, 

You can find a spice model for the LM56 on EasyEDA:

http://easyeda.com/project_view_The-EasyEDA-LM56-model_YWQ8qkCUc.htm

which shows how to use the model.

The model includes a pin called TEMP. This is a voltage input to represent temperature scaled in 1V/degC. This is so that it is easy to run the device in a transient simulation with a voltage source providing a dynamic temperature input so that the device behaviour can be seen directly in the time domain.

The subckt for the LM56EE is included in the spice netlist for the schematic.

There are two ways to view the spice netlist:

• To view the spice netlist of the schematic at any time:

1. 1. Save the schematic;

   2. Super Menu > Miscellaneous > Netlist for Document > Spice...

• To view the spice netlist after a simulation run:

1. 1. Green Man (Simulate...) > Simulation Results... > Download netlist

but in case you have trouble, here is a copy but please make sure that my pasting here has not corrupted it in any way (usually due to line wrapping):

*************************************************************
.SUBCKT LM56EE VREF VT2 VT1 GND VTEMP OUT2 OUT1 VCC TEMP
*************************************************************
**
* Behavioural model of LM56.
**
* Based on TI datasheet.
**
* This subckt models the basic switching and hysteresis
* behaviour of the device. It also models input bias current,
* quiescent current, input voltage range behaviour.
* Reference and VTEMP output voltage load regulation is
* crudely modelled but line regulation is not.
* The device effectively shuts down for supply voltages below
* 2.4V and draws excessive supply currents for supply voltages
* above Vabsmax (12V) and reverse supply connections.
* I/O pins are diode clamped to ground and supply rails.
* The temperature dependencies of internal device parameters
* such as reference voltage drift and bias current are not
* modelled.
**
* A TEMP pin (pin 9) has been added for a voltage representing
* temperature to be fed into the device.
* This allows the device to be used in transient simulations.
* This input has a resistance of 1G and must be connected to a
* voltage source scaled at 1V/degC; i.e. to represent a
* temperature of 25degC, a voltage source set to 25V must
* connected to the TEMP pin of the device.
**
* Developed for EasyEDA by signality.co.uk
**
* Last edited 150414
**
*************************************************************
* Datasheet params
.param
+ Ibias=150n ; A
+ Iq=230u ; A
+ Vabsmax=12 ; V
+ tempscale=6.2m ; V/degC
+ toffset=395m ; V
+ hys=5 ; degC
+ rout=1k ; Ohms (typ based on 1.5k max)
+ ref=1.25 ; V
**
* Model params
**
+ Vmin=2.4 ; V
+ gain=10k
+ IUP=200u ; A. Max output current from ref source
+ Ibase=10u ; A
+ Ivmax={10*Iq} ; A
********************
**
* Missing ngspice functions (comment out if using LTspice)
**
.param pi = 3.141593
.func LIMIT(x, y, z) {min(max(x, min(y, z)), max(z, y))}
.func PWR(x,a) {abs(x) ** a}
.func PWRS(x,a) {sgn(x) * PWR(x,a)}
.func stp(x) {u(x)}
*******************
**
* The circuit
**
* I/O clamping, resistances and capacitances
**
RDUMMY1 GND TEMP 1G
D14 GND OUT1 D
D15 OUT1 VCC D
D16 GND OUT2 D
D17 OUT2 VCC D
D18 GND VREF D
D19 VREF VCC D
D20 GND VTEMP D
D21 VTEMP VCC D
D6 GND VT2 D
D5 VT2 VCC D
RPAR5 VCC VT2 1G
C5 VT2 VCC 1p
D4 GND VT1 D
D3 VT1 VCC D
RPAR4 VCC VT1 1G
C4 VT1 VCC 1p
D2 GND D2_C D
D1 GND D1_C D
**
* Quiescent and input bias currents
**
B10 VCC GND I=Iq*V(vcc_ok)
RPAR6 GND VCC 1G
C6 VCC GND 1p
B9 VCC VT2 I=Ibias*V(vcc_ok)
B8 VCC VT1 I=Ibias*V(vcc_ok)
D13 GND VCC DVMAX
**
* VTEMP source with temperature scaling and offset
**
B7 GND VTEMP I=(V(temp,gnd)*tempscale+toffset)/rout
RPAR3 GND VTEMP {rout}
C3 VTEMP GND 1p
**
* Output stage drive
**
B6 GND D2_C I=(1-V(temp1_ok)*2)*Ibase*V(vcc_ok)
B5 GND D1_C I=(1-V(temp2_ok)*2)*Ibase*V(vcc_ok)
**
* Output transistors
**
Q2 OUT1 D2_C GND NPN
Q1 OUT2 D1_C GND NPN
**
* Current limited VREF source
**
B4 VREF GND I=0.5*((0+IUP)*TANH((V(vref,gnd)-ref)*1k)+(0-IUP))*V(vcc_ok)
RPAR8 GND VREF 1G
C8 VREF GND 1p
**
* VCC OK source.
**
B3 GND VCC_OK I=LIMIT(V(vcc,gnd), 0, Vmin)/Vmin
RPAR7 GND VCC_OK 1
C7 VCC_OK GND 1p
**
* VT1 and VT2 input comparators with hysteresis.
**
B2 GND TEMP2_OK I=0.5*( tanh( ( (LIMIT(V(VT2,GND), V(GND), V(VCC)-1)-V(VTEMP)) +
+ (V(temp2_ok)-1) *hys*tempscale )*gain )+1)
RPAR2 GND TEMP2_OK 1
C2 TEMP2_OK GND 1p
B1 GND TEMP1_OK I=0.5*( tanh( ( (LIMIT(V(VT1,GND),V(GND) , V(VCC)-1)-V(VTEMP)) +
+ (V(temp1_ok)-1) *hys*tempscale )*gain )+1)

RPAR1 GND TEMP1_OK 1
C1 TEMP1_OK GND 1p
**
* Models used
*************
.model D D
.model NPN NPN
.model Dvmax D Is=1e-12 N=2 BV={Vabsmax} IBV={Ivmax} Rs=450m
**
.ENDS
*************************************************************

The model is written for ngspice but will run in LTspice with the lines in the "Missing ngspice functions" section commented out. It should also run in PSpice with the same edits.

(Please note that the polarity inversion of the open collector outputs that you spotted in your post to EasyEDA has now been corrected.)

   :)

      Andy