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TINA/Spice/TPS50601-SP: How to choose compensation value / predict bandwidth when IC is used in a master/slave interleaved set?

Part Number: TPS50601-SP

Tool/software: TINA-TI or Spice Models

I am looking to define the bandwidth/phase margin of the TPS50601 used in the interleaved mode using two ICs.I have the TINA average model for one part. For the interleaved case Is it accurate to use a second IC model in parallel. (with a separate inductor per IC).

  • Hi Timothy,

    I will discuss your query with the team and will get back to you on this.

    Thanks & Regards,
  • Timothy,

    Yes that is correct you can use second IC model in parallel with separate inductor etc.
    You must make sure there is only one feedback loop ( master if you are operating at 500kHz and using internal clock)
    Comp pin of Phase 1 must be connected to comp pin of Phase 2
    Vsense of phase 1 must be connected to Vsense of phase 2
    Sync phase 1 must be connected to sync of phase 2
    RT pin of Master must be left open ( not populated) then sync pin will be an output
    RT pin of slave must be populated with proper switching frequency.
    SS pin of phase 1 can be connected to SS pin of phase 2
    Enable pin of phase 1 / connected to enable pin of phase 2 thus there is only one enable.
    Hope this addresses your concern.