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TINA/Spice/TPS543C20: TINA Model export from Webench

Part Number: TPS543C20
Other Parts Discussed in Thread: TINA-TI,

Tool/software: TINA-TI or Spice Models

Hi,

I am sorry I have not replied.
It is a question about TINA's simulation model that Saket-san corresponded before.
I attach a simulation model.
TPS543C20_2PH_20180621.TSC

I wanted to change the output voltage from 1.0 to 0.72 V, I added resistance to VSEL pin and RSP / RSN pin of U1 (Master), but I can not change the output voltage.

Also, it seems that the signal pin of U2 (Slave) is different from the wiring at 2phase operation. (When PGD pin is set to Open, an error message appears.)

Could you please fix these?

Best regards,
Yuto Sakai

  • Hi Yuto San,


    It seems that the parameter VREF_PASS has been used to program output voltage. Changing it to 0.72 will do the task here. PFA Tsc file and simulation results.3343.TPS543C20_2PH_20180621.TSC

    I am not clear with your 2nd question. We should not left a pin open. if you do not want use PG pin, then just connect a jumper as shown in below.

    Please let me know if you any other questions.

    Regards,

    Saket

  • Hi Saket-san,

    Thank you for your support.
    Is it specification that Iout and Iload are not measured?
    I actually did the simulation, but these current value did not come out.

    Best regards,
    Yuto Sakai

  • Hi Yuto-San,

    You can measure ILOAD and IOUT and both should be same as they are connected in series.

    The PWL Load current profile in above test bench draws 0A till 1.5ms and that is the reason you are not able to see any current in waveform.

    You can see the output current if you replace load with a resistance.(R4 in below diagram)

    Below are the simulation results.

    Regards,

    Saket

  • Hi Saket-san,

    Thank you for your kind surpport.
    I am sorry, but I will ask you two more question.
    I simulated the following TINA file.

    TPS543C20_2PH_20180705.TSC

    Q1:
    I changed the resistance value of the VSEL pin, but as a result of the simulation, the output voltage was not changed.
    Is it impossible to simulate by changing the output voltage? Could you respond to this?


    Q2:
    Previously, regarding the pin arrangement on the slave side in 2 phase configuration, I received an answer as shown below.

    At that time I heard that the RSP.RSN pin is open.
    However, if you open it with TINA, simulation will result in an error.
    Would you please fix it if possible?

    Best regards,
    Yuto Sakai

  • Hi Yuto-San,

    Please see my comments below in red.

    Q1:

    I changed the resistance value of the VSEL pin, but as a result of the simulation, the output voltage was not changed.

    Is it impossible to simulate by changing the output voltage? Could you respond to this?

    Saket: The Parameter VREF_PASS has been used to program output voltage in TINA model and the functionality of VSEL pin is not active. 

    Q2:
    Previously, regarding the pin arrangement on the slave side in 2 phase configuration, I received an answer as shown below.

    Saket: Yes, you are correct these pins are floating in actual device but model doesn't depict this behavior. I think model will need an update to take care of this feature.

    As of now, you can tie the RSP pin to VOUT and RSN to GND in order to regulate 2 phase.

    Please let me know if you have any other queries.

    Regards,

    Saket

     

  • Hi Saket-san,

    Thank you for your kind surpport.

    Is it ok to understand that it is not possible to change the reference voltage of the device by changing the resistance value of the VSEL pin?
    When changing Vout, is it only to change the resistance value connected by Vout - RSP - RSN (GND)?

    I understood the processing of the RSP - RSN pin on the Slave side.
    Please let me know if you can fix it.

    I appreciate your help.

    Best regards,
    Yuto Sakai

  • Hi Yuto-San,

    Below are my comments.

    Is it ok to understand that it is not possible to change the reference voltage of the device by changing the resistance value of the VSEL pin?

    Saket: Yes.

    When changing Vout, is it only to change the resistance value connected by Vout - RSP - RSN (GND)?

    Saket: As per my understanding, we do not need any resistance or need to change any resistance between these pins. You can refer to 2-phase EVM attached below. The RSP pin can be tied to VOUT directly and RSN to GND. The device uses VSEL pin to program output voltage.

    sluubl7.pdf

    I understood the processing of the RSP - RSN pin on the Slave side.
    Please let me know if you can fix it.

    Saket: We will need some time to update this model. I will get back on this in couple of days.

    Thank you for your patience and your valuable time spent in evaluating this model for 2-phase !

    Regards,

    Saket

  • Saket-san,

    Thank you for your kind surpport.
    Since the reference voltage is set at the VSEL pin,
    I think that it is possible to set the output voltage with the feedback resistor (Vout - RSP - RSN).
    In the EVM user's guide, the TSP543C20 on the Slave side has the RSP pin open.
    It will be greatly appreciated if it becomes possible to modify the above and change the output voltage to the use case.
    Either way, I appreciate your support.

    Best regards,
    Yuto Sakai