I am trying to create a design in FPGA Power Architect and have trouble with the power sequencing. As per Xilinx Kintex-7 device datasheet:
The recommended power-on sequence is VCCINT, VCCBRAM, VCCAUX, VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on.
However this is not what FPGA Power Architect suggests, it seems to think VCCINT and VCCBRAM don't need to be sequenced. When I try to change this and include them in the sequencing I can't seem to be able to modify the sequence. Is there a documented way to modify the sequence?
Thanks,
Valentin
Hi Valentin,
Thank you for your interest in Texas Instruments power solutions.
The sequencing requirements for this part were based off the original datasheet, thank you for bringing this update to our attention; I should have the new requirements in by next week. Also, the sequencing diagram has a bug that does not allow the user to adjust the order, we are currently working on a fix for this.
We appreciate your time, your patience and your feedback on this issue,
Regards,
Tommy Jewell
WEBENCH Apps TI