WEBENCH® Tools/TPS5450: Wrong date assigned to Power Designer designs; consistency of simulation results

Part Number: TPS5450

Tool/software: WEBENCH® Design Tools

Hello,

I'm testing the new Power Designer Webench tool and have found that all the designs have wrong time stamp. All the new one (that I've been working on last few days) as well as some older ones (weeks and months back) show wrong date. The shown month is January 2018 (instead of July), while the date seems to be correct. For example, the design that I've started today has assigned date "13 January 2018", where the number 13 is correct but the month should be rather July.

Also the simulation results are not consistent and when I ran the same design next day I got different results (Phase margin in this specific case). I do not want to go into details as it would be for separate thread. It does not convince me I can rely on the simulation results and calculations. The Phase margin calculated in "CUSTOMIZE" section is significantly different (sometimes!) than the same value shown in SIMULATE section.

Is the new version of Power Designer  preliminary or test build? Or is it still under development? I haven't seen such notification anywhere.  

Thank you.

Best Regards,

Josef Rýpar

5 Replies

  • Hi Josef,

    Thanks a lot for taking the time to test out the tool and provide your feedback to us.

    Someone from the team will get back to you on this post with regards to the date issue and new tool build status.

    I wanted to get more details from you on the bode plot phase margin mismatch issue you are mentioning here. Would it be possible to share details on that? Possibly share the design using public URL option for the design before and after so we can find out the root cause. If it just one design, then please share the public design URL and we can find out why simulate section results are different from the customize view.


    Regards,

    Amod

  • In reply to Amod Vaze:

    Hi Josef,

    The date issue has been fixed now. Please let me know if you have any questions on that.

    Regards,
    Amod
  • In reply to Amod Vaze:

    Hi Amod,
    please find here the link to the design.

    This time I've used the standard simulation environment (not the new Power Designer) and it seems the behaviour is similar.
    e2e.ti.com/.../2611921

    SImulations simId=1&5 are identical apart from feedback resistors (10k+5.9k vs 14k+8.2k) and are performed with capacitor 680uF/13mOhm . The calculated phase margin 61deg corresponds nicely with simulated 60.5deg.
    Simulations simId=2,3,4 are identical to simId=5 apart from output capacitor. I've tried varying the ESR of output cap: 0.01, 0.02, 0.025 Ohm. While the calculated phase margin is about 56deg, the simulated is only 40deg. And it almost does not change with ESR change.
    It looks like the simulation is extremely sensitive to the Cout ESR value.

    I've also calculated the whole design using equation in datasheet (TPS5450-EP) and I based on the equation [7] the fCO is 13.3kHz for 680uF, 10uH, 500kHz and Vout=3.3V. The simulated crossover frequency is two times higher (simId=3: 26.995kHz).

    Please review the results of the Webench Power Designer and let me know if you find any issues.

    Regards, Josef
  • In reply to Josef Rypar47:

    Hi Josef,

    Could you please share the design for which you are observing this issue.

    Please find the steps to share the design.

    1) Login into ti.com

    2) Click on the Share Design Tab

    3)  Click on Share with Public

    Thanks and Regards,

    Atul.

  • In reply to Atul Kulkarni23:

    I'm sorry, I thought that I've already shared the link, but I shared a wrong one.

    Here is the right link:
    webench.ti.com/.../SDP.cgi