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WEBENCH® Tools/TPS5450: Wrong date assigned to Power Designer designs; consistency of simulation results

Part Number: TPS5450

Tool/software: WEBENCH® Design Tools

Hello,

I'm testing the new Power Designer Webench tool and have found that all the designs have wrong time stamp. All the new one (that I've been working on last few days) as well as some older ones (weeks and months back) show wrong date. The shown month is January 2018 (instead of July), while the date seems to be correct. For example, the design that I've started today has assigned date "13 January 2018", where the number 13 is correct but the month should be rather July.

Also the simulation results are not consistent and when I ran the same design next day I got different results (Phase margin in this specific case). I do not want to go into details as it would be for separate thread. It does not convince me I can rely on the simulation results and calculations. The Phase margin calculated in "CUSTOMIZE" section is significantly different (sometimes!) than the same value shown in SIMULATE section.

Is the new version of Power Designer  preliminary or test build? Or is it still under development? I haven't seen such notification anywhere.  

Thank you.

Best Regards,

Josef Rýpar

  • Hi Josef,

    Thanks a lot for taking the time to test out the tool and provide your feedback to us.

    Someone from the team will get back to you on this post with regards to the date issue and new tool build status.

    I wanted to get more details from you on the bode plot phase margin mismatch issue you are mentioning here. Would it be possible to share details on that? Possibly share the design using public URL option for the design before and after so we can find out the root cause. If it just one design, then please share the public design URL and we can find out why simulate section results are different from the customize view.


    Regards,

    Amod

  • In reply to Amod Vaze:

    Hi Josef,

    The date issue has been fixed now. Please let me know if you have any questions on that.

    Regards,
    Amod
  • In reply to Amod Vaze:

    Hi Amod,
    please find here the link to the design.

    This time I've used the standard simulation environment (not the new Power Designer) and it seems the behaviour is similar.
    e2e.ti.com/.../2611921

    SImulations simId=1&5 are identical apart from feedback resistors (10k+5.9k vs 14k+8.2k) and are performed with capacitor 680uF/13mOhm . The calculated phase margin 61deg corresponds nicely with simulated 60.5deg.
    Simulations simId=2,3,4 are identical to simId=5 apart from output capacitor. I've tried varying the ESR of output cap: 0.01, 0.02, 0.025 Ohm. While the calculated phase margin is about 56deg, the simulated is only 40deg. And it almost does not change with ESR change.
    It looks like the simulation is extremely sensitive to the Cout ESR value.

    I've also calculated the whole design using equation in datasheet (TPS5450-EP) and I based on the equation [7] the fCO is 13.3kHz for 680uF, 10uH, 500kHz and Vout=3.3V. The simulated crossover frequency is two times higher (simId=3: 26.995kHz).

    Please review the results of the Webench Power Designer and let me know if you find any issues.

    Regards, Josef
  • In reply to Josef Rypar47:

    Hi Josef,

    Could you please share the design for which you are observing this issue.

    Please find the steps to share the design.

    1) Login into ti.com

    2) Click on the Share Design Tab

    3)  Click on Share with Public

    Thanks and Regards,

    Atul.

  • In reply to Atul Kulkarni23:

    I'm sorry, I thought that I've already shared the link, but I shared a wrong one.

    Here is the right link:
    webench.ti.com/.../SDP.cgi
  • In reply to Josef Rypar47:

    Hi Josef,

    On the bode plot issue -

    The values you observe in the "Op Vals" tab are based on a simple series R-C circuit for output cap. However, the "Sim" model uses more complex netlists for the 680uF 10,20, and 25mohm tantalum caps used in sim ids 2,3 and 4. You could use a "Aluminum" capacitor type while creating a custom output cap to simulate something similar to a simple series R-C circuit in order to compare "Op Vals" and "Sim". I have done that and created sim ids 6, 7, and 8 for the 3 different output caps. The results look closer to the "Op Vals" output now.

    Equation 7 in the datasheet seems like an approximation which might work out in some specific design conditions. However, the "OpVals" and "Sim" models are based on structural voltage mode control behavior so they should predict the response more accurately in different design conditions.

    Here is the shared design with additional sim ids 6,7 and 8 for your reference.
    webench.ti.com/.../SDP.cgi


    Regards,
    Amod
  • In reply to Amod Vaze:

    Hi Amod, 

    thank you for the explanation. If I understand correctly the simulator uses four basic capacitor models for these capacitor technologies: Ceramic, Aluminium, Tantalum, Polarized. Then the parameters like capacitance, ESR, voltage, current, temperature, tolerance are applied to the selected model and simulated. Is that correct?

    In my design I have selected 680uF / 18mOhm Kemet capacitor T530X687M006ATE018 which is a Polymer Electrolytic capacitor. Which model (from the four models above) represents this technology the best?

    I've simulated these values (680uF, 18mOhm) with all four technologies (CER, AL, TA, POL) and found that the CER, AL and POL give practically identical phase margin (65.393, 65.382, 65.485) while the TA gives a phase margin that is a way out of the others: 40.773. The difference is so big that it makes me to doubt whether the simulation with TA is really correct. https://webench.ti.com/appinfo/webench/scripts/SDP.cgi?ID=C186BF88A440EF53

    What I want to say. Normally designers select the outputs capacitors (for this kind of application) based on the two key parameters: Capacity and ESR (let's put aside voltage and current ratings that does not affect stability in simulation). This simulation demonstrates that this is not enough and I shall consider something else, which is hidden in your TA capacitor model that is not obvious and may not be searchable in datasheet. This also means that the calculations shown in the datasheet does not lead to design with good stability margin when TA output capacitor is used.

    Could you please indicate which property of TA capacitors causes the phase plot to differ so much from the three other technologies?

    Please comment the above thought flow and provide answers to bold questions.

    Thank you for your support.

    Best Regards,

    Josef Rypar

  • In reply to Josef Rypar47:

    Hi Josef,

    You are right on the model types: Ceramic, Aluminium, Tantalum and Polarized. We only account for voltage bias related variation on the caps. No temperature and tolerance variations included at this point.

    I found out that we typically use simple R-C model for bode plot simulations in the tool. However, this device has a bug and we are using the complex R-C models instead which are supposed to be used only for transient simulations. We will work on fixing this issue.

    At this point, I would recommend using the "Polarized" model as that is simply an R-C model under the hood for your bode plot simulations. If you are specifically looking for a model for T530X687M006ATE018, the closest model would be the model from Kemet themselves. I do see that Kemet has a K-Sim tool in which you can enter the part number and acquire a SPICE model. However, unfortunately, bode plot standalone model is not enabled for this device so you might not be able to simulate this with the SPICE model from Kemet but you can surely verify the transient performance. The standalone model can be downloaded via the "Sim Export" tab within the design.

    Hope this helps.

    Regards,
    Amod

  • In reply to Amod Vaze:

    Hi Josef,

    We wanted to make sure you got all answers to your questions.

    1. As you see above, the timestamp issue has now been fixed, and you should be able to refer to your archived designs.

    2. We have responded to the bode plot question above. We can start a separate thread if you’d like to discuss that further.

    3. We consider the new version of Power Designer a Beta version, and functionally equivalent to the old Flash version. We would like to invite you to try out the new version and give us feedback on what you think in terms of usability and features, and any issues you may come across. We have an active development roadmap, and are committed to adding new features to the new version.

    Please let us know if you have more questions.

    Regards,
    Amod
  • In reply to Amod Vaze:

    Hi Amod,
    I'm quite satisfied with provided answers and I don't have any open issue now. However I would appreciate if you let me know when the bug with TA caps described above is fixed. It is not critical or urgent, just for my info.
    I like the new version of Power Designer and seems to be slightly more intuitive and easier to use. One thing that I would suggest to improve is a manipulation with bode plots - make it easier to turn the gain+phase traces on and off, especially if there are 4 and more bode plots in one graph. I know it is possible to turn them selectively on and off but this controls shall be one-click accessible.

    Thank you for your support.

    Regards, Josef

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