WEBANCH LM43603

Hi Eli,

Looks like the IC temperature calculated is limiting your maximum frequency. WEBENCH is using the thetaJA value for the IC from page 5 of the datasheet (38.9degC/W). On the evaluation board, the effective thetaJA is most likely lower because of the copper on the layout of the board that helps with heat dissipation.

A workaround may be to lower the ambient temperature (Ta) for the WEBENCH design to offset the increased heat dissipation calculated in WEBENCH.

See below customer feedback/question

I had to go down to 0°C to be able to set F=500kHz. I’ll just assume it’s a simulation problem… 

Anyway, I am trying to determine the effect of the output capacitance on output ripple and on Iout step response (Iout=1.5A ® 3A).

I tried to compare two values for Cout:

• 220uF, ESR=15mΩ, Q=1
• 47uF, ESR=5mΩ, Q=3

The 3x47uF capacitors have much lower ESR so I assumed the output ripple and step response will be noticeably better. However, this does not seem to be the case according to the Webench simulation; on the contrary, ripple and step response seem a little worse. 

What is reason for these results?

I found the first capacitor used (220uF, ESR=15mΩ, Q=1).

I tried looking for the second capacitor combination (47uF, ESR=5mΩ, Q=3) in the list of alternate BOM components but could not find it, so I wasn't able to run the load transient. The ripple and step response discrepancy may be an issue with the capacitor model - WEBENCH simulation sometimes uses different output capacitor models depending on the part number.

See below:

1)      I defined a custom ceramic capacitor:

Although under the “Simulation Spice model” I selected Ceramaic, it keeps reverting to Polar. I will also share the design with you.

1)      Am I correct in my general assumption, that with 3 x 47uF output ripple and step response should be better?

http://webench.ti.com/webench5/power/webench5.cgi?DesignId=336&base_pn=LM43603&app=

I think you may be right - specifying the model type for the CUSTOM capacitor in the drop-down menu is not used properly. I will let the software team know.

Unfortunately there's not a good way to define a custom netlist for capacitor right now in the WEBENCH electrical simulator.

You can see exactly what model is being used by using the "Export" button to export the simulation. Here is the TINA-TI simulation schematic for your design:

3678.webench_design_1242494_2428.tsc

4062.webench_design_1242494_2427.tsc

"Enter Macro" shows the netlist used for the output cap model.

Here are the output cap models in case you can't access the TINA-TI software:

***********************************
*     Created by WB Importer      *
***********************************
.SUBCKT MAIN_BLOCK_Cout_WB_CAP_AL 2 4
R1 2 3 0.015
C1 3 1 2.2E-4 IC = 0.0
R3 5 4 150; "free space" reduced by sqrt(dielectric constant)
R2 2 4 4545454.545454545
R4 3 26 1.8749999999999998E9
R6 3 7 1874.9999999999998
C5 7 1 8.800000000000001E-5 IC = 0.0
R7 3 10 1874.9999999999998
C6 10 1 8.800000000000001E-5 IC = 0.0
R8 3 13 1874.9999999999998
C7 13 1 8.800000000000001E-5 IC = 0.0
C2 26 1 8.800000000000001E-5 IC = 0.0
R9 3 28 1.8749999999999996E7
C3 28 1 8.800000000000001E-5 IC = 0.0
R10 3 29 187499.99999999997
C4 29 1 8.800000000000001E-5 IC = 0.0
L8 1 5 0.2e-9
R24 1 5 0.045
L12 5 4 10e-12
.ENDS

***********************************
*     Created by WB Importer      *
***********************************
.SUBCKT MAIN_BLOCK_Cout_WB_CAP_OUTPUT 13 2
* Steve's Tantalum Model w/Initial Conditions

* C=1.4099999999999998E-4 F
* ESR@1K=0.0016666666666666668 Ohm
* ESL=8.0E-9 H
* RLEAK=1000000.0 Ohm
* IC=0.0 V

C3 13 11 1.7624999999999998E-5 IC=0.0
C4 13 3 8.812499999999999E-6 IC=0.0
C5 13 4 4.4062499999999995E-6 IC=0.0
R1 4 5 0.0020833333333333333
R2 3 6 0.0015
R3 11 7 0.002916666666666667
R4 12 8 0.0038666666666666667
C6 13 9 7.049999999999999E-5 IC=0.0
R5 13 0 1000000.0
R6 9 10 0.010416666666666668
L1 5 2 8.0E-9
L2 6 2 8.0E-9
L3 7 2 8.0E-9
L4 8 2 8.0E-9
L5 10 2 8.0E-9
R8 2 0 1000000.0
C2 13 12 3.5249999999999996E-5 IC=0.0
.ENDS

So your simulation with 3x 47uH 5mohm is using 8nH of parasitic ESL, which may be causing the additional ringing and overshoot.

Your general assumption that a smaller ESR should result in a smaller output ripple is correct. I think the poor step response may also be because of the ESL.

assume TINA-TI cannot be used for the Iout step simulation I want. Am I correct?

eli,

What kind of Iout step simulation do you want to perform? TINA-TI has configurable current sources that can be set up to simulate most any Iout pulse you desire.

Britt

Hi

want to simulate Iout step response: Iout=1.5A ---->3A ® -------> 1.5A.

Eli,

Place a PWL current source (Current generator) in parallel with your load.

Set up your resistive load for 1.5A and then configure your PWL load to provide an additional 1.5A after the circuit has reached steady state.

Run the simulation to see the results.

Britt