WEBENCH® Tools/UCC28C43-EP: flyback design circuit evaluation

Hello Leela,

I believe the problem may lie in the feedback path. The schematic diagram that you posted has low resolution so it is difficult to read the reference designators and component values, but some of them seem clear enough to be able to discuss them.

1. Your feedback loop appears to have 2 compensation blocks, one at the TL431 regulator and one at the UCC28C43 COMP pin. But the values are the same, so I suspect that these are simply place holders. The UCC28C43-EP datasheet does not have any application information, but the UCC28C43 datasheet does. I recommend that you re-arrange the feedback network (from TL431 to COMP input) to similar to that as shown in Figure 31 (page 24) of the UCC28C43 datasheet (non-EP version).

2. Then use the application section of that datasheet to a. verify you power-stage component value design, and b. follow the loop-compensation procedure to calculate the appropriate values for your circuit. The example in the UCC28C43 datasheet applies to a single-output 48-W design, but the same procedure should be followed using input parameters that apply to your project. In a multi-output design, usually one output is regulated directly (in this case, the +15V output) and the power levels of the other outputs are referred to the regulated output. The capacitances of each output are translated to the regulated output by the turns-ratios squared.

3. The resistor in series with the opto-coupler photodiode is unclear whether it is 470 ohm or 47K ohm, but 470 ohm is too low and 47K is too high for the current that the phototransistor will need to handle. The design procedure should result in the appropriate value.

4. In the existing arrangement, the emitter of the opto-coupler feeds into a resistor divider which results in a voltage at FB_A which cannot go higher than VREF/2 even if the saturation voltage of the phototransistor = 0. Therefore the voltage at the FB pin is always less than the internal reference voltage of 2.5V, and this will always drive COMP to its maximum value and drive full duty cycle under any line and load condition. This would result in over-voltage on the outputs unless an OV protection circuit is activated. It is my guess that this is what the other opto-coupler U21 does and pulls down on COMP when the secondary-side LPS_OK_DSP signal is driven high, maybe due to output OV detection? As a result, the system would appear to periodically "hiccup", or cycle on and off, without steady state regulation. I recommend to remove R172 (the bottom of the divider) to allow FB_A to rise above 2.5V and then COMP can go low without assist from U21.

5. The filter capacitor on the CS input appears to be 1000pF and the series resistor R150(?) looks like 1K or something. This adds a 1-us time delay to the CS signal which results in higher peak current per switching cycle. This makes the feedback loop work harder to respond to load transients and reduces stability, because the delay adds unwanted phase shift to the loop response.
I recommend to reduce the CS capacitor to 100pF to start. During prototype debug, you can optimize the total RC product to be only as large as necessary to squelch possible noise at CS, but no more than necessary to avoid adding significant delay and phase shift.

I hope this helps you make progress on your design.

Regards,
Ulrich