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Table of contents for DLP Discovery™ 4100 evaluation module frequently asked questions.
1. How much power does the kit/chipset require?
The amount of power consumed by the chipset in the DLP Discovery™ 4100 evaluation module is highly use-case dependent, which is why a number is not provided in the datasheet for the DLP devices. Parameters such as speed, block resetting, and application can heavily impact the amount of power consumed by the kit.
2. How much optical power can the DMD handle?
One common question is how much power the DMDs can handle optically. In the datasheets for these devices, in table 7.4, you'll find the recommended operating conditions.
The illumination power depends on the wavelength as well as the thermal management of the system. Each DMD has a range of wavelengths for which the window is optimized. Using illumination outside of those wavelengths typically reduces the ability of the DMD to handle high power because of losses in the window. The term "thermally limited" means the device can handle a given optical power density provided the system-level thermal solution keeps the DMD within its specified operating temperature range. As an example, the DLP9500UV has the following spec:
2 mW/cm^2 (<363 nm)
2.5 W/cm^2 (363 - 400 nm)
11 W/cm^2 (400 - 420 nm)
Thermally limited (>420 nm)
For further information, read Wavelength Transmittance Considerations for DLP® DMD Window: www.ti.com/lit/pdf/dlpa031
3. Does the DLP Discovery™ 4100 GUI work on 64bit Windows?
Yes, with the release of the DLP Discovery 4100 GUI version 1.1, support is included for 7 & 8, 32 bit as well as 64 bit.
4. Where can I find example apps FPGA code for the DLP Discovery kit?
There is a basic applications FPGA code example posted online to generate patterns that will display using the DLP Discovery 4100 kit.
Go to the DLP Discovery 4100 tool folder, and see the download link listed under Software Files.
Here is the description of functionality listed in the ReadMe file:
Automatically generates patterns that display on a Discovery 4100 EVM
Allows testing via on-board switches of:
· Float mirrors
· Pause / Resume pattern display (halts Apps FPGA internal counter)
· Compliment data & N/S flip
· Single, Dual, Quad & Global block mode mirror clocking pulses
· Automatic row counter and Ros address mode loading
· Enable / Disable mirror clocking pulse watchdog timer
Please take the time to search the E2E forum as well. In the past users have posted example code for others to use - this can also be a great resource.
5. What type of input does the DLP Discovery™ 4100 use?
The DLP Discovery™ 4100 is Texas Instrument's most flexible and powerful DLP® technology platform. It allows users the lowest level control over the DMD and as such, the data coming into the controller is simply binary data. The user interface for the application will have to be built handle RGB or Grayscale data such that it is fed to the device correctly. Please consult the datasheet and associated technical literature on the DLPC410 for further information.
6. What is the difference between "Global" and "Phased" resets?
With the DLP Discovery™ 4100, there are two modes for resetting the mirrors - Global and Phased.
A global reset impacts all the mirrors on the DMD. During this type of reset, it is not possible to load data to the DMD as the mirrors are resetting.
A phased reset does one block of mirrors at a time. Each block needs 12.5us to settle, during which you may not load data to that block. You may however send data to other blocks while a given block is being reset.
Please consult the datasheet for the DLPC410 and the user's guide for the DLP Discovery™ 4100 for further information.
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