Other Parts Discussed in Thread: DLPDLCR4710EVM-G2, , DLPC3439
Dear Philippe,
I think I might misinterpret TI guidelines.
Regarding your comment about the first option describing the mapping options:
MASTER ASIC:
------------------
M_HS_WDATA_D_P --> D_AP(0)
M_HS_WDATA_D_N --> D_AN(0)
M_HS_WDATA_C_P --> D_AP(1)
M_HS_WDATA_C_N --> D_AN(1)
[...]
M_HS_WDATA_E_P --> D_AP(7)
M_HS_WDATA_E_N --> D_AN(7)
SLAVE ASIC:
------------------
S_HS_WDATA_D_P --> D_BP(0)
S_HS_WDATA_D_N --> D_BN(0)
S_HS_WDATA_C_P --> D_BP(1)
S_HS_WDATA_C_N --> D_BN(1)
[...]
S_HS_WDATA_E_P --> D_BP(7)
S_HS_WDATA_E_N --> D_BN(7)
And taking into consideration the following table:
Should it be the following a correct configuration?
MASTER ASIC (option 2 guideline):
------------------
M_HS_WDATA_E_P --> D_AP(0)
M_HS_WDATA_E_N --> D_AN(0)
M_HS_WDATA_F_P --> D_AP(1)
M_HS_WDATA_F_N --> D_AN(1)
M_HS_WDATA_G_P --> D_AP(2)
M_HS_WDATA_G_N --> D_AN(2)
[...]
M_HS_WDATA_C_P --> D_AP(6)
M_HS_WDATA_C_N --> D_AN(6)
M_HS_WDATA_D_P --> D_AP(7)
M_HS_WDATA_D_N --> D_AN(7)
AND FOR
SLAVE ASIC(option 1 guideline):
------------------
S_HS_WDATA_D_P --> D_BP(0)
S_HS_WDATA_D_N --> D_BN(0)
S_HS_WDATA_C_P --> D_BP(1)
S_HS_WDATA_C_N --> D_BN(1)
[...]
S_HS_WDATA_E_P --> D_BP(7)
S_HS_WDATA_E_N --> D_BN(7)
I have the following schematic on my DMD4710 chip design, I will appreciate if you can give it a look and tell me if I am right. What would happen if I connect it this way?