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DLPD4X00KIT: active_cnt in APPS FPGA sample code

Part Number: DLPD4X00KIT

Hi, 

I have been trying to modify the APPS FPGA sample code to change the patterns displayed on DMD with the DLP 4100 Kit.

With the following code in pgen_a, I expected 16 vertical strips that the ON and OFF alternatively. However, the DMD display showed only 8 vertical strips. Any specific reason for this?

The resolution of the DMD used is 1024 by 768 so that only data buses A and B are utilized.

							IF cnts_active_cnt_q2(0) = '0' THEN
								douta_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
								doutb_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
								doutc_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
								doutd_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
							ELSE
								douta_temp1 <= x"0000000000000000" AFTER 1 PS;
								doutb_temp1 <= x"0000000000000000" AFTER 1 PS;
								doutc_temp1 <= x"0000000000000000" AFTER 1 PS;
								doutd_temp1 <= x"0000000000000000" AFTER 1 PS;
							END IF;

Thanks for your help.

Qiang

  • Hi Qiang,

    Welcome to DLP section of TI E2E community. I will get back shortly to you with details.

    -ykc
  • Hi Qiang,

    I am working on this. Will get back to end of this week. Meanwhile I see from your other queries you need to load custom images and need delay.

    I would suggest you a better alternative "DLPLCR6500EVM ". This controller has inbuilt DRAM to store 400 1 bit 1080p patterns and GUI to load images in RAM and configure delay for each pattern. 

    This will speed up your development.

    -ykc

  • Hi ykc,
    Thanks for your information and suggestion.
    I will think about using the DLPLCR6500EVM as an alternative.

    Actually, for the current DLP 4100 Kit, I'm able to switch the patterns with the CASE statement.
    The variable pgen_row controlling the rows works as expected.
    My only problem now is the working of active_cnt (3 DOWNTO 0), which controls the columns. My understanding is that it gives 16 clock cycles. But it doesn't work as expected. As I mentioned in the code, the DMD shows only 8 vertical strips.

    In my understanding, the time delay or the time interval between two patterns is controlled by the time takes to change pattern1. For example, from "000" to "001".
    Since pattern 1 <= cnts_pattern_cnt (26 DOWNTO 24) and cnts_pattern_cnt is increased by 1 in rising edge (in cnts module), the number of time periods takes is 2^(24) * clk_period. The clock period is 20 ns with frequency of 50 MHz so that the time delay is 2^(24) * 20 ns = 0.1677 s.

    Is this correct?

    Thanks,
    Qiang
  • cnts_pattern_cnt increase by one after one cycle of active_cnt is finished not on each clock.

    -ykc

  • I see. So cnts_pattern_cnt increases by one after 16 clock cycles.

    So the time delay is 2^(24) * 20 ns * 16 = 2.68s?

    I have been thinking about why I got only 8 vertical stripes instead of 16. In the cnts module, I found the following process

    --active counter keeps track of 16 cycles of valid output data
    PROCESS (clk_g, locked_init_rstz_gq)
    BEGIN
       IF (locked_init_rstz_gq = '0') THEN
          active_cnt <= "0000";
       ELSIF clk_g = '1' AND clk_g'event THEN
        IF reset_del_q(3) = '0' THEN -- added for sync reset
          active_cnt <= "0000";
        ELSE -- added for sync reset
    
         IF active_cnt = "0111" THEN
           active_cnt <= "0000";
         ELSIF active_cnten = '1' THEN
           active_cnt <= active_cnt + 1 AFTER 1 PS;
         END IF;
    
        END IF ; -- added for sync reset
       END IF;
    END PROCESS;

    It seems that active_cnt is reset to "0000" when it reaches "0111". So it only allows 8 different numbers.

    Qiang

  • Yes. Its split into 2 processes pattern1 and pattern2

    -ykc
  • Hi ykc,

    Is there any update on the active_cnt? 

    Thanks,

    Qiang

  • Discovery4100_verticallines.zipHi Qiang,

    I had problem with using Xilinx platform cable with Windows 10 PC. It is not supported. I am attaching files. These are based on new version of this code available on web. I have made changes to display vertical lines. I could see vertical lines alternate every 16 columns on WXGA DMD.
    Just load appsfpga.bit in your hardware and see if you are able to see 16 columns on and 16 col off alternatively.

    I have made changes in pgen_a.vhd PROCESS (clk_g, locked_init_rstz_gq)
    -ykc

  • Hi ykc,

    Thanks for the files.

    I loaded the .bit file and the DMD really showed 16 columns ON and 16 columns OFF, with a column width of 32.

    However, this doesn't solve my problem since I want to use the variable cnts_active_cnt_q1 (or q2, q3) to control the columns.

    In your code, the following section controls the pattern generation.

    ELSIF clk_g='1' AND clk_g'event THEN
    		 douta <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
    		 doutb <= x"0000000000000000" AFTER 1 PS;
    		 doutc <= x"0000000000000000" AFTER 1 PS;
    		 doutd <= x"0000000000000000" AFTER 1 PS;

    But what if I want to have 8 columns ON and 8 columns OFF, with a column width of 64 pixels?

    Thanks,

    Qiang

  • Hi Qiang,

    Try this

    8 pixel on 8 off
    douta <= x"FFFFFFFF00000000" AFTER 1 PS;
    doutb <= x"FFFFFFFF00000000" AFTER 1 PS;
    doutc <= x"0000000000000000" AFTER 1 PS;
    doutd <= x"0000000000000000" AFTER 1 PS;

    You can simulate this design in ISE to see how various signals behave.

    -ykc

  • Hi ykc,

    Thanks for the suggestion.

    I actually misunderstood the meaning of columns.

    What I would like to realize is N pixels ON and N pixels OFF, where N > 16.

    For N <= 16, it can be realized by modifying douta and doutb.

    That's why I really want to understand the working of active_cnt.

    I'm confused since we have 16 clks per row (32 clk edges) while active_cnt is allowed to change from 0000 to 0111, only 8 numbers.

    Could you please clarify this for me?

    Thanks,

    Qiang
  • Hi Qiang,

    active counter is run twice per row. There is a blanking counter between 2 runs. You can simulate the design. PFA the simulation.

  • Hi ykc,

    Then it makes sense. I just want to control each cycle individually.

    In my current version FPGA sample code (downloaded from www.ti.com/.../DLPD4X00KIT), I don't have the blank counter in the cnts module.
    Would you mind sharing the project file you used for simulation?

    I tried to do the simulation with the testbentch file, but not sure about the stimulus for inputs.

    Thanks for your help.

    Qiang
  • Software.zipHi Qiang,

    Blankcounter is present in previous version also. Please look for cnts_a_1and16clks.vhd file.

    PFA the project. tb_pgen.vhd

  • Hi, ykc,

    Thank you so much for the files.

    You mentioned that active_cnt is run twice per row. But the simulation shows only once.

    For each row, the blank counter runs first, and then the active counter, as shown in the figure below.

    This is actually consistent with my observation. With the condition of cnts_active_cnt_q (0) = '0', the DMD shows vertical strips with 128 pixels ON and 128 pixels OFF alternatively, since 1024 / 8 = 128.

    IF cnts_active_cnt_q(0) = '0' THEN
        douta_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
        doutb_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
        doutc_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
        doutd_temp1 <= x"FFFFFFFFFFFFFFFF" AFTER 1 PS;
    ELSE
        douta_temp1 <= x"0000000000000000" AFTER 1 PS;
        doutb_temp1 <= x"0000000000000000" AFTER 1 PS;
        doutc_temp1 <= x"0000000000000000" AFTER 1 PS;
        doutd_temp1 <= x"0000000000000000" AFTER 1 PS;
    END IF;

    So how can generate vertical strip with 64 pixels ON and 64 pixels OFF?

    In general, how to control each column of the DMD matrix?

    Thanks for your considerations.

    Qiang

  • Hi Qiang,

    Yes you are correct. I will get back to you tomorrow with project to change individual column bits.

    -ykc
  • column.zipQiang,

    PFA the project to control each column bit. Search for dmd_line_a and dmd_line_b in pgen_a. It has comments for which bit corresponds to which pixel within a row.

    -ykc

  • Hi ykc,

    Thanks for your files. 

    But dmd_line_a and dmd_line_b just provide control over 8 segments for each row. The width of each row is 128 pixels.

    This can also be realized using the active counter, which allows 8 numbers.

    I still have the problem in generating 64 pixels ON and 64 pixels OFF, as shown in the figure below.

    Could you please give some comments on how to generate such a pattern?

    Thanks,

    Qiang

  • Hi Qiang,

    Have you used the project I sent you ? Default settings in it is to generate the pattern you are asking. 64 pixel on 64 pixel off.
    Each row is 1024 bit.
    Each entry in dmd_line_a is 64 bit . You have to use first 8 entries = 64* 8 = 512
    Similarly dmd_line_b = 64 * 8 = 512
    Total = 1024 bits
    Comments says which bit is which pixel.

    type DMD_LINE_ARRAY is array (0 to 31) of std_logic_vector(63 downto 0); -- Longest Line is 1280
    SIGNAL dmd_line_a : DMD_LINE_ARRAY := (
    x"FFFFFFFF00000000", -- 0-15 32-47 64-79 96-111
    x"FFFFFFFF00000000", -- 128-143 160-175 192-207 224-239
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000", -- 896-911 928-943 960-975 992-1007
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000"
    );
    SIGNAL dmd_line_b : DMD_LINE_ARRAY := (
    x"FFFFFFFF00000000", -- 16-31 48-63 80-95 112-127
    x"FFFFFFFF00000000", -- 144-159 176-191 208-223 240-255
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000",
    x"FFFFFFFF00000000", -- 912-927 944-959 976-991 1008-1023
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000",
    x"0000000000000000"
    );
  • Sorry. I misunderstood the code. It works as you mentioned.

    I thought x"FFFFFFFF00000000" is 16 bit, but actually 64 bit.
    Now I think I'm able to generate arbitrary patterns.

    Really appreciate your help and patience.
    Thanks,
    Qiang