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DLPC910: Control signal skew requirements

Andrew Holme
Prodigy 140 points
Part Number: DLPC910

We want to use DLP6500 + DLPC910. The display daughter card in our legacy system has 40 LVDS I/O and 39 LVCMOS33 GPIO.  We need 36 LVDS pairs for DCLKIN_A, DCLKIN_B, DVALID_A, DVALID_B, DIN_A[15:0] and DIN_B[15:0] leaving 4 spare LVDS pairs.  We need many LVCMOS25 signals for ROWAD, ROWMD, BLKAD, BLKMD.  We need to level shift from LVCMOS3V3 to LVCMOS25.  DLPC910 datasheet says ROW*/BLK* should assert and de-assert synchronously with DVALID.  Timing skew requirements are very tight: +/- 100ps maximum skew between CLKIN_n and ROW* / BLK*.  It is difficult to find level shifters with propagation delay / skew specs good enough to meet this.  Do you have any suggestions?  Do the edges of the single-ended control signals really have to align within 100ps of the LVDS transitions?

  • 0
    Prodigy 140 points
    DLPC910 datasheet says VCCO_1 and VCCO_3 should be 2V5. Must they?
  • 0 in reply to Andrew Holme
    TI__Expert 4530 points

    Hi Andrew,

    Yes you have to follow spec for proper operation. I will check if I found any recommendation for you.

    -ykc

  • 0 in reply to ykc
    Prodigy 140 points

    Banks 1 and 3 only contain digital I/O connected to the APP FPGA correct?  And the DLPC910 is really just a Virtex 5 right?  Why is it not possible to change VCCO_1 and VCCO_3 to 3V3?  This would allow us to drive it directly from our legacy FPGA.

  • 0 in reply to Andrew Holme
    TI__Expert 4530 points

    Hi Andrew,

    Yes, Banks 1 and 3 IOs are connected to apps fpga only. And its Virtex 5.
    I checked datasheet for vcco_1 and 3 you can go till 3.45V. 

    So you should be fine using 3.3V for these. banks.
    -ykc

  • 0 in reply to ykc
    Prodigy 140 points

    Understood.

    Another option for us would be to setup ROW* and BLK* inputs before DVALID is asserted.  Will this work?  Datasheet says they must be "asserted and de-asserted synchronously with DVALID" but, the stated skew requirements are extremely severe, making this hard to do in practice.  When / how often are these signals sampled internally, relative to DVALID / DCLK edges?  Should the timing requirements for these signals not be like COMP_DATA and NS_FLIP with just a setup and hold requirement relative to the DCLK edge?  A related question is: relative to which DCLKIN_n edge is the ROW* and BLK* skew to be measured? All of them?

    Thanks,

    Andrew.

  • 0 in reply to Andrew Holme
    TI__Expert 4530 points
    Hi Andrew,

    You can use 3.3V for vcco_1 and 3 as per datasheet it can go til 3.45V in recommended operating section. Can you point me where you see max 2.5V?

    Yes you can set row* blk* before dvalid asserts. row* and blk* are common for all 4 buses.

    -ykc
  • 0 in reply to ykc
    Prodigy 140 points

    Thanks.  I will proceed with 3V3 for VCCO_1 and VCCO_3.  That is the simplest solution for us.  We may also adjust the timing of our signals to ensure that ROW* and BLK* are settled and valid slightly before DVALID.  We can experiment with that.