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  • TI Thinks Resolved

CCS/DLPC410: RST_ACTIVE is not asserted regularly

Intellectual 265 points

Replies: 26

Views: 1301

Part Number: DLPC410

Tool/software: Code Composer Studio

Hi,

Our setup is as followed: (Virtex7, DLPC410, DLP7000)

https://e2e.ti.com/support/dlp/f/94/p/759718/2806469

As we have resolved the previous problem, the DLPC410's initialization and calibration go successfully, and we can also retrieve the right DMD_TYPE and VERSION. However, the control outputs somehow couldn't get to the mirror, and I'll list some of our observation below:

1. The RST_ACTIVE stays low even after we output BLK_MD = 11, BLK_AD = 1000, ROW_MD = 00, ROW_AD = 'd0, and other control signals (e.g. wdt_ena, rst2blkz, ns_flip ...) weren't toggled during the output.

2. ECP2_M_TP16 (Clock reset) stays high after initialization. We're not sure if this is normal and what causes this if it is not.

Thanks,

Justin

  • Expert 4340 points
    Hi Justin,

    Welcome to DLP section of TI E2E community.
    Please check clocks. It is likely the PLL settings and ranges are different between the 5 and 7 series families.

    -ykc
  • In reply to ykc:

    Hi,
    All the PLLs are locked on both APP_FPGA and DLPC410. We also checked the system clock on TP4, and it is a working 200MHz clock.
    Justin
  • Expert 4340 points

    In reply to Justin Chen14:

    Justin,

    What is the timegap between consecutive commands?

    -ykc
  • In reply to ykc:

    Hi,

    We followed the datasheet to wait for the micromirror settling time. And as mentioned in the previous post, our code worked before.

    Justin
  • Expert 4340 points

    In reply to Justin Chen14:

    Justin,

    Please see sent command is as per Figure 11 of www.ti.com/.../dlpc410.pdf
    Dvalid is high for 16 clock cycles.

    Also can you provide scope shot of these signals from first dvalid rising to next command dvalid rising.

    -ykc
  • In reply to ykc:

    Hi,

    Yes, we kept DVALID high during the whole operation (>16T).

    We could not fetch output ports with ILA, but we can provide our simulation. The interval between the 2 markers is 16T.

    Thanks,

    Justin

  • Expert 4340 points

    In reply to Justin Chen14:

    When you say Reset active is not asserted regularly, is there any pattern to it.
    Like every alternate command is not asserting or it is failing after certain number of commands.

    -ykc
  • In reply to ykc:

    Hi,

    I should express it more precisely, the "rst_active" is always low no matter I send a global reset command to DLPC410 or not.

    Thanks,

    Justin
  • Expert 4340 points

    In reply to Justin Chen14:

    Hi Justin,

    Thanks for clarification. Please let me know status of

    ECP2_M_TP28 (pin G10)

    -ykc
  • In reply to ykc:

    Hi,

    It's a steady logic low

    Thanks,

    Justin

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