Other Parts Discussed in Thread: DLPC150
I have read the DLPA0008 document and it shows the buffer size for a XGA DMD. See this image:
I am trying to find this same information for the WVGA version, DLP2010NIR. The DLP2010NIR is 854 pixels wide and our team was unsure if it would require 32 clock edges or less (32-bits*27= 864 pixels > 854).
Our team is trying to preform a raster scan as fast as possible. We are trying to determine the maximum speed at which a single pixel (or small group of pixels) could be scanned across the DMD if the display is loaded row by row with the DLPC150 controller IC and utilizing the max speed 75 MHz 24-bit parallel interface. Based on what we have read so far the minimum total time to toggle a single pixel appears to be:
(6uS (micro mirror switch time) + time the load the row on the SubLVDS 532 MHz bus + time to transfer data to DLPC150 on 24-bit parellel bus @ 75 MHz) x 2
x2 because you would need to enable the pixel and then clear it again before moving to the next pixel. We have seen 2880 Hz binary pattern rate in multiple sources. Although this is quite fast to display a pattern we need to raster each micro mirror much faster than this.
Thanks,