Part Number: DLPC3439
Hi,We have an issue with our custom board which is based on reference designfor the DLP4710 LightCrafter. There are different opinions on the supportforum regarding connection of the sub-LVDS between DMD and DLPC3439 in caseof dual ASIC use:https://e2e.ti.com/support/dlp/f/94/p/730365/2700616#2700616https://e2e.ti.com/support/dlp/f/94/t/741486https://e2e.ti.com/support/dlp/f/94/t/657816Some say we must use only one configuration for both DLDC3439 chips, andothers say that different configuration should be used.By now we have a board with the same routing (Option1 - Slave) of sub-LVDSsignals for master and slave. And there is only the half of DLP4710 workingproperly and displaying images. This working half is connected to slaveDLPC3439. Other half (master connected) only shows non-periodic bars ofdifferent intensity. Their appearance depends on splash screen or testpattern selected, they can change width and intensity, but nothing close toreal image. We have tested the two of manufactured boards and they behavethe same way.All power supplies look good, LEDs are enable and no system errors isreported. With Read System Status (D1h) command we get:Master vs. Slave Operation - 0h: MasterIs that abnormal display functioning is the result of our signal routingconfiguration or something else? If yes can our problem be fixed with a newfirmware? Or is the retracing of pcb the only way to get system workingproperly.Regards, Maxim Galkin
As per explanation looks like you have used different pin mapping. Could you please share the schematic to review. I am sending you friend request on e2e, you can share your schematic in private message.
FYI, please use this thread for correct mapping : https://e2e.ti.com/support/dlp/f/94/t/657816
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In reply to Navneet Singh:
Hi Navneet, Thank you for your fast reply! We can’t share the full schematic but only a part. We are sending a pdf document where connection between DLP4710 and master and slave DLPC3439 are shown. Based on the thread you are referring to, our schematic looks the same – pin mapping for maser and slave ASIC corresponds to Option 1. We are using the latest firmware from TI. Is it appropriate for our pin mapping?
In reply to Maxim Galkin41:
Ti.com firmware is for option2. you are using the option 1. I am not sure how you are getting the half image correct.
i can not see any pdf document from your side to review. Please send it in private message.
once confirm we will provide you the firmware with option1.
DLPC3439 master-slave connection to DLP.pdf
I reviewed your design and i can understand your confusion with the mapping.
We are updating our datasheet to provide the better explanation like we did in this datasheet for which i am providing the link below....
You need to change your mapping in the following manner mentioned in the datasheet below : http://www.ti.com/lit/ds/symlink/dlpc3479.pdf Table 10, Page 45 ( section 8.3.11).
Please let me know if anything is not clear to you..
Thank you! Now we can see our mistake and why only the half of the DLP is working properly. To be sure we should rework pin mapping for the master so it will be:HS_WDATA_E_P ‑ Input DATA_p_0HS_WDATA_E_N ‑ Input DATA_n_0HS_WDATA_F_P ‑ Input DATA_p_1HS_WDATA_F_N ‑ Input DATA_n_1……HS_WDATA_D_P ‑ Input DATA_p_7HS_WDATA_D_N ‑ Input DATA_n_7 and in case of slave pin mapping will stay without changes from our design:HS_WDATA_D_P ‑ Input DATA_p_0HS_WDATA_D_N ‑ Input DATA_n_0HS_WDATA_C_P ‑ Input DATA_p_1HS_WDATA_C_N ‑ Input DATA_n_1……HS_WDATA_E_P ‑ Input DATA_p_7HS_WDATA_E_N ‑ Input DATA_n_7 Am I right? Then we can use firmware file dpp3439-dual-ASIC_7.3.2?And there is no way of changing firmware so it will make the system work correctly with the full image on the DLP display with our actual pin mapping?
Yes you are right. you can use firmware available on ti.com.
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