Hi,
We have build a DLPC3437 projection platform and may mass production in this month.
We also have a frond end controller that can output TTL format image signal to FPGA XC7Z020 TTL input port (include DLPC3437 reference design).
I would like to confirm the FPGA XC7Z020 TTL input port format and clarify define.
I need to know the TTL clk and TTL data is " CLK Low to High trigger data" or " CLK high to low trigger data" ?? which one is correct??
Clock low to high then trigger data
Clock High to low then trigger data
