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DLPC410: Interface training pattern

Allen Lin19
Prodigy 30 points
Part Number: DLPC410

Hi,

Designed a DLP controller board with DLPC410. I read "Interface training pattern" from DLPC410 datasheet. 

1. Does the interface training pattern implement by APPSFPGA(User FPGA)?

2. Does the input signal ARSTZ of DLPC410 must hold to low until INIT_ACTIVE is asserted? 

3. APPSFPGA should send pattern "0010" continuously until INIT_ACTIVE is deasserted?

  • 0
    TI__Mastermind 43185 points

    Hello Allen,

    First, welcome to the DLP section of the TI-E2E forums.

    1. You are correct that the interface training patterns must be sent by the APPS_FPGA (i.e. User FPGA):
      1. This is already done by the Pattern Generator version that loads at startup.  The source for this can be loaded from the DLPD4x00KIT page.  It will let you see how it is implemented.
      2. The GUI version also does the same.
    2. Yes the DLPC410 must be held in reset (assert ARSTZ) until APPS_FPGA begins sending the training patterns.
    3. Yes the APPSFPGA should continuously send training patterns until the DLPC410 deasserts INIT_ACTIVE (i.e. initialization has finished.

    Fizix