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DLPC910: About clear / reset control of DLPC 910

Part Number: DLPC910

It is a question about clear / reset control of DLPC 910 (DLPR 910 A).

Since the timing requirements of BLKMD / AD (LVCMOS 25) and DCLK are severe as shown in Fig.1, I would like to change BLKMD / AD within DVALID as shown in Fig.2.

Is there no problem?

DLPC910 DataSheet (P16)

http://www.tij.co.jp/jp/lit/ds/symlink/dlpc910.pdf 

Fig.1

Fig.2

  • Hello User,

    Welcome to the TI-E2E forums and the DLP section of the forums.

    We will have to study the proposed implementation.  Have you tested this timing with the controller?  If so, does it work?

    We will try to have guidance on your question on Wednesday or Thursday (June 27 or 28).

    Fizix

  • Hello Fizix

    Thank you for the reply.

    >Have you tested this timing with the controller? If so, does it work?
    I have not tried it yet.

    Up to now, DCLK and BLK_AD / MD were running at the same time, but the operation was not stable.

    Ueda
  • Hello Ueda-san,

    When you say that the operation was not stable, could you give more details.  

    Are you attempting to send continuous row operations?  If so, please see the application note here:

    DLPC910 / DLPR910A - Continuous Row Command Operation 

    You are welcome to test the proposed operation, but since it does not follow the datasheet specifications, we cannot guarantee that it will work.

    Fizix

  • Hello Ueda-san,

    Please give more details about "the operation was not stable". We need more information in order to attempt to provide a solution.

    Fizix
  • Hello Fizix

    I am sorry that the reply was delayed.
    Commands such as reset are not stable. .
    After setting the command signal first, setting DVALID to High later will work.

    I believe that the nature of the signal may be the cause.
    DVALID and DCLK are LVDS (fast changeable), but BLK_AD / MD is LVCMOS 25 (change later than LVDS)

    >Are you attempting to send continuous row operations?

    Yes. I am about to attempting to send continuous row operations

    >You are welcome to test the proposed operation, but since it does not follow the datasheet specifications, we cannot guarantee that it will work.

    I understand

  • Hello Ueda-san,

    Please let us know the result. you may also try moving it the other direction (i.e. two clocks after D-valid start).

    Fizix
  • Hello Fizix

    I'm sorry.
    The cause is under investigation, but even if DVALID and BLK_AD / MD are changed at the same time from the FPGA on the operation side, it is stable and it works now.

    Thank you for your response.

    Ueda
  • Hello Ueda-san,

    Thank you for letting us know. If it is stable and works then continue with that setup.

    Fizix