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Internal Video from Internally Generated Patterns

Other Parts Discussed in Thread: DLPC300

Dear TI staff,

I am developing original LightCrafter board which does not have PFGA and DM365 CPU.

By the document DLPU004A (DLPC300 Programmer's Guide) section 2.3.1.3 (Internal Video from Internally Generated Patterns) and by Table 2-115 (Steps to Configure DLPC300 for Internal Video Mode with Internally Generated 1-bit Vertical Patterns), I sent I2C commands to DLPC300. But internal patterns are not displayed.

How can I display internally generated patterns?

Please teach me.

Best regards,

Alex

  • Alex,

    Sorry for the delay answering.

    Could you send a list of the I2C commands which you send to the DLPC300? Include all the steps.

    Are you able to read back registers? Are you sure that the I2C transactions are working?

  • Pascal,

    Thank you very much for your response.

    The answers are;

    1. I2C transaction is working.

    2. I can read back registers. Writing subroutine write value to a register then read back the register and verify.

    3. Attached is the diagram of my board and I2C command list. The "Test Value" column is I2C commands I sent.

    Please check it.

    Best regards,

    Alex


  • Alex,

    I will have this checked. It may take a bit of time. Thank you for your patience.

  • Pascal,

    Thank you very much for your reply. I am waiting for your analisys result.

    And my fundamental concern is if I can display internal generated patterns w/o FPGA and DM365.

    Best regards,

    Alex

  • Hello Alex,

    Sorry for keeping you waiting.

    The internally generated patterns are 1bit patterns ONLY. There is mistake in the documetation, in the Table 2-115 the reference to Table 2-80 is for the step #8 wrt sequence selection is not correct. The Table 2-80 os used for External Color Video sequences only.

    Instead of Table 2-80 you should select Table 2-114, the sequence number = 17, start vector = 0, sub-vector = 9.

    Let me know if you see the images with this configuration.

    Regards,

    Sanjeev

  • Sanjeev,

    Thank you very much for your reply. This is a very important information. I will test this soon and report the result.

    Best regards,

    Alex

  • Sanjeev,

    I changed the configuration as your suggestion, then the internal test pattern images were displayed!

    Thank you so much.

    The display period of each pattern is 16.6ms (60Hz).

    Can I change its frequency by some configuration (slower or faster)?

    Please teach me.

    Best regards,

    Alex

  • Hello Alex,

    Actually the 1-bit patterns hold as long as you want. The display sequence jumps to next pattern only after receiving the trigger signal.

    What it means is that you can send the trigger signal with periods ranging from 250us to anything.

    Regards,

    Sanjeev

     

  • Sanjeev,

    I misunderstood that w/o FPGA design, pattern rate is 60Hz max.

    I am going to change my circuit and send trigger to display faster.

    Thank you.

    Regards,

    Alex

  • Hi Sanjeev, is this also the case when using 1b mono with preload patterns (DLPU004B, 2.3.1.2.8 1-bit Internal Video Sequence with Optional FPGA)? What is this trigger signal?

    In internally generated pattern mode, does it still need FPGA to rotate the buffer? It looks like the maximum is 32 1b patterns which is > 1 frame buffer (24 bit planes).

    In both video modes, how should we set the following registers when we want FPGA to control the pattern exposure time?
    1. Video Frame Rate control (0x19)
    2. Sequence Sync Mode (0x1E)

    In both video modes, is the trigger output still available to control camera exposure?

    Thanks,
  • Hello William,

    Where did you see the reference to 32 1b patterns? Buffer is still 24 bit planes.

    1. Video Frame Rate Control - Not applicable in pattern mode.

    2. Sequence Sync Mode (0x1E) = 0x01 set to lock to VSYNC in both streaming mode or pre-loaded pattern mode (FPGA still sends sync signal to jump across the buffer).

    Trigger output is coming from the FPGA as processed signal; the FPGA modify the signal coming from DLPC300.

    Regards,
    Sanjeev
  • "Where did you see the reference to 32 1b patterns? Buffer is still 24 bit planes. "

    My question was for the mode where patterns are internally generated by DLPC (refer DLPU004B, 2.3.1.3). I believe you have 15 different patterns (with inversion option) to choose from, and the max pattern set is 32 frame deep. Therefore, that's 32 1-bit planes at maximum.

    1. I'm wondering in this mode, what does the FPGA need to do? Since the Sequence Sync mode is still set to lock-to-VSYNC, so I guess VSYNC is still required?

    2. How to control the pattern exposure time in this mode? What are the exposure limits?

    3. Is there still a trigger output from DLPC in this mode?

    4. Table 2-115 in DLPU004B, step 8 still ask for preload images? Isn't patterns internally generated by DLPC?

    Again..thanks so much for your continuous support!
  • DLPU--4B, 2.3.1.3 - There is a HW block inside the DLPC300 that is capable of generating the pattern directly, it doesn't go through the 24-bit frame buffer.

    1, Yes

    2, For 1-bit, Pattern exposure are generated by the FPGA, since there is only 1-bit to be shown, after loading this data on the DLP3000 the LED_EN signals can be shown for any time (in this case it is upt 2.0), this signal is generated by the FPGA.

    3, Yes

    4, documentation mistake, actually Section 2.2.8 Internal Pattern Generator commands used to configure the pattern to be displayed, there is no need of step #8, instead we must use 2.2.8 commands to select the registers.

    Quick question - Is the Internal Generated patterns Figure 2-4 and Figure 2-5 is sufficient enough for you then, you can look at the GUI tool to know patterns are configured.

    Regards,
    Sanjeev
  • Yes, the Figure 2-4 and Figure 2-5 are sufficient enough for now. I have to get opinions from our software engineers on those patterns. Thanks!