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Buffer Rotation Timing

Other Parts Discussed in Thread: DLPC300

Hello,


I have a question on how to rotate the circular Buffer of the DLPC300. In the fpga overview document the wave forms of the HSYNC,VSYNC and DATEN signal are given, but unfortunately without any timings.
The text says to send 800 pixel per line with 608 active pixel. How long are the horizontal front and back porch? And long do the HSYNC and VSYNC pulses need to be? Is there a recommended pixel clock frequency?
Kind regards
Martin

  • Hello Martin,

    The text says to send 800 pixel per line with 608 active pixel. How long are the horizontal front and back porch?

    [Sanjeev] You have the flexibility here, as long you are within the min and max spec, mentioned in DLPC300 controller datasheet http://www.ti.com/lit/ds/symlink/dlpc300.pdf Table 8. Parallel Interface Frame Timing requirements.

    And long do the HSYNC and VSYNC pulses need to be?

    [Sanjeev] Same as above, VSYNC >= 1 line, HSYNC b/w 4pixel clocks to 128 pixel clocks.

    Is there a recommended pixel clock frequency?

    [Sanjeev] Anything b/w 1MHz - 33.5MHz

    One important topic - 

    Once you are done with getting the frame timing, it is very important that the DLPC300 register must be configured as per the frame time-setting, you can refer to 2.2.2 Parallel Interface Configuration and Control registers of the controller chip.

    below are the sample timings for generation -

    Resolution native - 608x684

    Pixel Clock : 32 MHz
    Horizontal:
    Active Time : 608 Pixels
    Blanking Time : 124 Pixels
    Sync Offset : 40 Pixels
    Sync Pulse Width: 32 Pixels
    Border : 0 Pixels
    Frequency : 43 kHz

    Vertical:
    Active Time : 684 Lines
    Blanking Time : 45 Lines
    Sync Offset : 10 Lines
    Sync Pulse Width: 4 Lines
    Border : 0 Lines

    Digital Separate, Horizontal Polarity (+), Vertical Polarity (+)

    Resolution WVGA 854x480

    Pixel Clock : 30.24 MHz

    Horizontal:
    Active Time : 854 Pixels
    Blanking Time : 96 Pixels
    Sync Offset : 40 Pixels
    Sync Pulse Width: 16 Pixels
    Border : 0 Pixels
    Frequency : 31 kHz

    Vertical:
    Active Time : 480 Lines
    Blanking Time : 45 Lines
    Sync Offset : 10 Lines
    Sync Pulse Width: 2 Lines
    Border : 0 Lines

    Digital Separate, Horizontal Polarity (+), Vertical Polarity (+)

    Let us know if anything not clear.

    Regards,

    Sanjeev

  • Hello Sanjeev,

    thank you for your reply. I have a few more questions:

     - What do you mean by Sync Offset?

     - What do you mean by Border?

    - What do you mean by digital seperate?


    I am trying to preload images for the "Pixel Accurate Video Mode with Preloaded Images
    with Optional FPGA" mode but I don't get the buffer to rotate.

    Kind regards,

    Martin

  • Hello Martin,

     - What do you mean by Sync Offset? - What do you mean by Border?

    [Sanjeev] Sync offset = Front-porch. The meaning changes with non-zero Border, since we have put it as zero. You can safely take SyncOffset = Front proch.

    - What do you mean by digital separate?

    [Sanjeev] You are expected to send both HYSNC and VYSNC on two separate lines. This is the normal way. Some digital interface can take composite sync i.e., both HSYNC and VSYNC signal on same line.

    Regards,
    Sanjeev

     

  • Hello Sanjeev,

    I tried to combine the information you gave me with the wave from from the fpga decription. Would the following signal pattern cause the buffer to rotate?

    I think I don't need to worry about the vertical blanking and offset times, because I need only one VSYNC signal to rotate the buffer. Is that correct?

    And is there any timing requirement for the falling edge of the VSYNC signal to the rising edge of the next HSYNC pulse (marked with '?')? Are both edges on the same pixel clock?


    Thank you very much for your help!

    Martin

  • Hello Martin,

    I tried to combine the information you gave me with the wave from from the fpga decription. Would the following signal pattern cause the buffer to rotate?

    The 124pix notation, is not clear to me,  

    Total Horizontal line => 608 + 124 pixels, i.e., before the raising edge of the next HSYNC, from the 124 pixel blanking time  32pixel is HSYNC pulse width, so remaining, (124-32) = 92pixels should be the time before raising edge of next HSYNC. 

    I think I don't need to worry about the vertical blanking and offset times, because I need only one VSYNC signal to rotate the buffer. Is that correct?

    [Sanjeev]   Yes you are correct.

    And is there any timing requirement for the falling edge of the VSYNC signal to the rising edge of the next HSYNC pulse (marked with '?')? Are both edges on the same pixel clock?

    [Sanjeev] Not additional timing is needed.

    Regards,
    Sanjeev

     

  • Hello,

    Can someone please help me with a problem I having with the DLP Lightcrafter.

    I am trying to generate 608 by 684 @ 60Hz using a Avent/Xilinx development board(ZED Board). To my knowledge I have generated the signals as per, further up, on this post.

    However what is displayed on the Light Crafter is half of the picture in the horizontal(as in the left side of the picture), but exactly correct in the vertical. I have then put the HDMI into a HDMI monitor and it displays the whole picture but reckons the picture is 1216 by 684 @ 60Hz. i.e. exactly twice the horizontal number of pixels.

    I'm very confused and hoping I'm doing something stupid or my understanding is wrong. Does anyone have any good idea of what I'm doing wrong. See below for my calculations and measurements of signals. All help would be extremely appreciated. Also note I generated 640 by 480 @ 60Hz and everything worked exactly as I expected.

    Stephen

    I am measuring the Hsync, and Vsync sent to the Analog Devices ADV7511(on the ZED Board) and they are as I think they should be. i.e. HSync has a pulse width of 1us with a period of 22.91us. Vsync has a pulse width of 92 us with a period of 16.7ms

    Pixel Clock period =1/(32000000) = 0.00000003125 secs.

    So Hsync PW is 32 * 31.25ns = 1 us

    Total Horizontal time is (608 +124) pixels * 31.25ns = 22.81us(i.e. almost what I measured) which is the same when accounting for measurement error.

    VSync PW is 4 lines = 22.81 * 4 = 91.24 us.(so again exactly what I measured accounting for measurement error)

    Total Vertical time is (684+45) lines * 22.81us = 0.1662849 s (again what I measured)

    Refresh rate = 1/(Total Vertical time) = 60.13775 Hz

  • As you can see the HMDI connected signals are going via FPGA on board before reaching to DLPC300. The DM365 configures FPGA for each mode, so please use and configure LightCrafter via GUI tool provided, make sure you are Display Mode = HDMI Video and HDMI Vide tab the Resolution is set as 608x684.

    Regards,

    Sanjeev

  • Hi Sanjeev,

    Thanks for your reply. I'm fully aware how to use the GUI. And it is setup for Display Mode = HDMI Video and HDMI Vide tab the Resolution is set as 608x684.
    When using a Windows PC to generate the 604 by 684 hdmi/dvi-d signal it also works correctly. I have no easy way of measuring that signal.

    As I said I need to generate the video from the ZED board. So I used the 608 by 684 settings of:

    Pixel Clock : 32 MHz
    Horizontal:
    Active Time : 608 Pixels
    Blanking Time : 124 Pixels
    Sync Offset : 40 Pixels
    Sync Pulse Width: 32 Pixels
    Border : 0 Pixels
    Frequency : 43 kHz

    Vertical:
    Active Time : 684 Lines
    Blanking Time : 45 Lines
    Sync Offset : 10 Lines
    Sync Pulse Width: 4 Lines
    Border : 0 Lines

    Digital Separate, Horizontal Polarity (+), Vertical Polarity (+)

    But it seems like I'm generating 1216 by 684 @ 60Hz but I don't understand why. According to my calculations and what I'm measuring it should equate to 608 by 684 @ 60Hz. I was just hoping that there might be something obvious or you'd seen something similar before and could go "Ah thats because you haven't taken account of something or you've forgotten about this etc,etc"

    Its not easy on a forum to describe my problem.

    Many Thanks for your time,

    Stephen
  • Hello Stephen,

    If you read http://www.ti.com.cn/cn/lit/an/dlpa042/dlpa042.pdf document. Figure-2, the DM365 generates such resolution 1216x684, in FPGA it will be converted back to native 684x608 resolution, where as the external incoming DVI video signal there is nothing much done in the FPGA, it will be bypass as it is. As you are mentioning, via GUI HDMI video is selected and also rcorrect esolution setting is applied, then you are mentioning the PC is able to detect and send proper resolution then it has to be something to do with your ZED board output. One more thing, can you also select, External Streaming Pattern Sequence, LED Select = any one Red/Green/Blue, Frame-rate = 60Hz, click on set, see if it makes any difference, if NOT, i suggest you to go back and look at the ZED board video timing, make sure it is 60Hz.

    Regards,

    Sanjeev