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DLPC300 input select issue

Other Parts Discussed in Thread: DLPC300, TFP401A

I am working on a design that has a micro HDMI port to a TFP401A, the 24bit pixel bus goes to a DLPC300. This is a custom board design. We are targeting a projector that is rated for 854x480, I took the EDID file from the eval board for this projector. I can display my desktop on this projectors eval kit.

I am having trouble displaying my desktop on the new custom design using the same projector. I can display a splash screen and a checkerboard pattern, but the parallel bus feed is not coming through. I am using the standard SPI flash load associated with the Lightcrafter.

When I plug my desktop into the HDMI port, I get the SCDT (link detect) to go high on TFP401A, and the clock, Vsync, Hsync, and DE, and data bits look similar to timing diagram in DLPC300 datasheet. The clock runs at approx 30Mhz, as the EDID indicates.  My PC changes the screen and when I look at display setting it says 854x480 on the pc. The projector continues to display a lightcrafter splash screen, but it does turn red when the HDMI port is plugged.

We are not using the DM365 or FPGA that is on Lightcrafter, so this application is basically a simple display of what is on HDMI port. 

The board also uses the same MSP430, so we have been modifying the standard Lightcrafter load to try and get it to work. In the code, we set the input to "parallel RGB", WVGA_854_Landscape (#19), and we have tried both RGB565 and RGB888 with no luck.

Is there any indicator in the DPLC that it's happy with the parallel bus? Any registers I can check to verify that the parallel bus is getting into the DLPC300.

If we can display splash screens and checkerpatterns, does it indicate our DDR memory is working? I see activity on the memory bus, but I need some indicator that its working. What is the BIST test that is mentioned in the programmers guide? 

The TFP401A is strapped for 1 clock/ pix operation, I do not see anything in DPLC resisters for this parameter. 

This design is approaching a deadline, so if someone can contact me, it would be much appreciated. 

  • Hello Arthur,

    Sure. 

    Is there any indicator in the DPLC that it's happy with the parallel bus? Any registers I can check to verify that the parallel bus is getting into the DLPC300.

    [Sanjeev]

    Make sure, the DLPC300 registers set with following values to configure the device in display from RGB parallel port.

    {Register, Data}
    { 0x82, 0x00 }, //Disable Sequencer
    { 0x1E, 0x01 }, //Sequencer Sync is input sync
    { 0x0D, 0x02 }, //RGB888 24bit Pixel format
    { 0xC3, 0x00 }, //Disable BTP/CHI/Y2R/SCL/DPF
    { 0x0B, 0x00 }, //Select Parallel RGB interface
    { 0x50, 0x07 }, //Enable Automatic Gain Control
    { 0x7E, 0x00 }, //Enable temporal dither
    { 0x5E, 0x01 }, //Enable Color Coordinate Adjustment
    { 0x82, 0x01 }, //Enable Sequencer

    I would expect you should see video from the port with this setting, 

    If we can display splash screens and checkerpatterns, does it indicate our DDR memory is working? I see activity on the memory bus, but I need some indicator that its working. What is the BIST test that is mentioned in the programmers guide? 

    [Sanjeev] yes, if the splash and test patterns are displayed properly, then mDDR is working fine. BIST for mDDR memory test, make sure it is reporting pass. 

    Let us know if anything else we can help you with.

    Regards,

    Sanjeev

  • I've been looking and cannot find what the BIST on the DLPC300 actually does to test the mDDR memory. Does it write a bunch of random values into the memory and read it back or something else?

    Thanks,

    Phillip

  • Hi Phillip,

    BIST as part of power-on-reset process, the controller write bunch of random values then compare to ensure mDDR is working properly. We seem to have disabled the BIST test to ensure faster power-up but I will check on that.

    Regards,
    Sanjeev