DPLC300: explanation on errors of the interrupt status register

CMB you mean Bit9 thru Bit11? DMD reset Bit1 through Bit3? Ideally these should not occur, all the interrupt registers are indication DLPC300 not configured properly..

Can you send us the steps we can see what could be going wrong.

Image Freeze or black cannot show this kind of error, it mostly happens when controller displaying data from mDDR to DLP3000 and the registers of DLPC300 not configured properly in this case.

Regards,
Sanjeev

Hi Bastien,

Are you still having issues? If so, could you reply to Sajeev's comments?

Thanks,
Clinton

Hi clinton and Sanjeev,

Sorry to answer so late but i was on vacation.

My request is to well understand each interrupt. ( it's not clear for me when i read the datasheet). I would like to know in which case interrupts could be raised (specially for the CMB and the DMD reset : how can those interrupts occur).

A small description will be very helpfull because I have to implement like an ISR so I need to well understand .

Regards,

Bastien

Hi Sanjeev,

Sorry to answer so late but i was on vacation.

My request is to well understand each interrupt. ( it's not clear for me when i read the datasheet). I would like to know in which case interrupts could be raised (specially for the CMB and the DMD reset : how can those interrupts occur).

A small description will be very helpfull because I have to implement like an ISR so I need to well understand .

Regards,

Bastien

Hi Bastien,

Are you referring to the DLPC300 programmer's guide (www.ti.com/.../dlpu004) section on these interrupts? If so, I can research these interrupts further to see if there are additional cause and effect details that we can provide.

To clarify, you are not seeing these interrupts, but are writing ISRs to handle scenarios where they occur, correct? If you are seeing these interrupts occur, please provide additional details on the steps you are taking that cause these interrupts to trigger.

Thanks,

Clinton

Hi Clinton,

To clarify, we're using the DLPC in a system with a FPGA and a µcontroller; we have a safety part managed by the FPGA, We need to know what's the impact of theses interrupts to shutdown or not the system. So that's why I need more explanations on causes and effects

I'm not seeing these interrupts but I have to implemented a safety road map for our system

I have read the DLPC300 programmer's guide but it's not enough/clear for my understanding, so can you provide me some additionnals details on cause and effect please?

Regards,

Bastien

Hi Bastien,

Thanks for the clarification on your use case. Sanjeev will be able to provide the best insight into this topic. He's been out on business travel, but I will make him aware that this thread is still open.

Thanks again,
Clinton

Hello Bastien,

On your comment "Specially for the CMB and the DMD reset : how can those interrupts occur"

Actually these are internal error and supposed to occur if the device is not running Sequence properly - note, the sequences and their associated configuration data (LUTs) resides in the Flash to which DLPC300 is connected. Now based on the I2C commands received the DLPC300 loads the relevent sequence and other LUTs from the flash.  

I would recommend everytime after applying new configuration to monitor the register and (whenever the flags set) when you do a write operation to the register the flags should be cleared, if the error flags remains persistent it is clearly indicating the issue in the configuration steps and procedure. So each error flag is important and any flag set clearly points to the configuration of the controller.

Unfotunately we can provide this much information only.

Regards,

Sanjeev