Hello,
I am looking at the D4100 dev kit with the 0.95" 1080P DMD for a prototype, but I am concerned about the single port access to the SODIMM DDR2 RAM.
I need to be able to run the mirror at just under 10,000 binary fps and be able to update the frames stored in memory during run time. From the documentation I have read, the development board can run the 1080P mirror at that frame rate, if all frames are already pre-stored in the RAM or an external PC can stream frames to the board at a much slower rate (24bit x 60hz = 1,440 binary fps).
Ignoring the data bandwidth limitation between the external PC and the development board, the problem seems to be that the development board was designed with a single port access to the SODIMM DDR2 RAM. Meaning that while the RAM is outputing frames to the mirror, it is not accessible to be updated.
Question 1: Can you confirm the above assumption?
To correct the issue, we would need to put a FIFO between the RAM and the mirrors and read data out of the RAM in blocks. Since I am not confident that the Virtex's FIFO could handle this due to the large amount of data, we may have to use a different FPGA development board that has dual port access to a SODIMM DDR2 port.
Question 2: If that were the case, will TI provide the schematics/layout files for at least the DMD mirrors/controller/reset portion of the board?
I have also read on the forum that the DDC4100 controller source code is proprietary. I assume the DDC4100 is TI's controller IC for the DMD's.
Question 3: If am I am developing my own FPGA core to provide data to the DDC4100 controller, should I be concerned about this?
Thank you.