I am looking at the D4100 dev kit with the 0.95" 1080P DMD for a prototype, but I am concerned about the single port access to the SODIMM DDR2 RAM.
I need to be able to run the mirror at just under 10,000 binary fps and be able to update the frames stored in memory during run time. From the documentation I have read, the development board can run the 1080P mirror at that frame rate, if all frames are already pre-stored in the RAM or an external PC can stream frames to the board at a much slower rate (24bit x 60hz = 1,440 binary fps).
Ignoring the data bandwidth limitation between the external PC and the development board, the problem seems to be that the development board was designed with a single port access to the SODIMM DDR2 RAM. Meaning that while the RAM is outputing frames to the mirror, it is not accessible to be updated.
Question 1: Can you confirm the above assumption?
To correct the issue, we would need to put a FIFO between the RAM and the mirrors and read data out of the RAM in blocks. Since I am not confident that the Virtex's FIFO could handle this due to the large amount of data, we may have to use a different FPGA development board that has dual port access to a SODIMM DDR2 port.
Question 2: If that were the case, will TI provide the schematics/layout files for at least the DMD mirrors/controller/reset portion of the board?
I have also read on the forum that the DDC4100 controller source code is proprietary. I assume the DDC4100 is TI's controller IC for the DMD's.
Question 3: If am I am developing my own FPGA core to provide data to the DDC4100 controller, should I be concerned about this?
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Welcome to the DLP section of the TI-E2E Community.
Answer 1: You are correct that the D4100 Evaluation kit design does not have dual port access to the memory, so that you can read or write but not simultanously.
Answer 2: Yes - Please contact the Design House that you are considering buying a D4100 kit or DDC4100 chipset from and request access to the DLP Extranet. After a brief screening process they will provide you with information on how to access the DLP Extranet. The schematics, USERS_FPGA source code and other documentation are available there.
Answer 3: If you are designing your own FPGA core with dual port memory access then this should not be a concern.
I hope this helps.
Is there any update about your problem? We have the same issue and we want to stream from PC.
If TI people can comment on it, we'll be appreciated. There are firmware updates supported by the design houses (such as ALP 4.1 high speed) but the problem is the size of the RAM. For high speed projection applications (e.g. 4800 bitplanes/sec), the RAM capacity is not enough (our binary video is about 10GB). So streaming from PC can solve that problem. However, if DVI or HDMI is used the default streaming capacity is 24bit @ 60 Hz = 1440 bitplanes/sec, which is not even close what is needed. So, is there a way to overcome that problem? Thanks,
The DDC4100 Chipset is capable of up to 17.6K binary FPS in global mode for a 1080p device. This will reach the speed you need, but there is no native way to input those frames. There is no off the shelf solution that you can plug in to reach the 10K binary FPS you need.
However, with the Virtex 5 (LX50) APPS_FPGA it would be possible to build a program that would interface to the EXP connector. It would be up to you to determine the best format for getting the data to the EXP connector and how to interpret it. This kit was designed as a development module with the idea that individual solutions would be created by the developer of the system.
You might check out WinTech's offering of a PCIe interface to their W4100 (based on the DDC4100 chipset and very similar to the D4100 dev kit). See --> http://www.ti.com/analog/docs/memsdlpdsgn.tsp?sectionId=622&tabId=2448#wintech
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