DLP & MEMS

Browse by Tags

DLP & MEMS

Welcome to the DLP & MEMS Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

Sign In to Post
Tags
You have subscribed to this tag. To view or manage your tag subscriptions, click here.   Close
You have unsubscribed from this tag. To view or manage your tag subscriptions, click here.   Close
You are currently viewing:
APPSFPGA DDC4100 DLP4100
Related Posts

  • Forum Post: RE: DLP4100 APPSFPGA 200MHz vs 400MHz

    Eyal Niv
    Thanks for responding. I do not have the Discovery Explorer GUI installed, however I do have the ALP software by ViALUX. I will try to look for the DDC4100 version in there. I haven't been able to measure the VBIAS rail yet. Is there a test point on the PCB where the voltage is easily accessible...
    on Aug 11, 2012

  • Forum Post: RE: DLP4100 APPSFPGA 200MHz vs 400MHz

    Eyal Niv
    By the way, Another discussion I started recently regarding this issue at Xilinx: http://forums.xilinx.com/t5/Timing-Analysis/minimal-skew-between-output-pads/m-p/254184#M3306 To summarize: different I/O standards: LVDS25 and LVCMOS25 are the main result of the SKEW. Not much I can do about it (Had...
    on Aug 11, 2012

  • Forum Post: RE: DLP4100 APPSFPGA 200MHz vs 400MHz

    Eyal Niv
    Thank you for clarifying that. I am still using the SERDES in the IOB and the LVCMOS inputs (to the DDC) are within 1/2 clock cycle so I guess this is not the reason for the 400MHz design inconsistent initialization. All row operations are synchronized to the rising edge of DCLK_IN except of the...
    on Aug 15, 2012

  • Forum Post: RE: DLP4100 APPSFPGA 200MHz vs 400MHz

    Eyal Niv
    Thank you, I did not have access to the DLP over the last few days, however, I assume that the voltages are fine since the ALP software from VIALUX works well with a 400MHz data rate. Therefore, there must be something wrong in my initialization. All the signals you mentioned (RST2BLKZ, COMP_DATA,...
    on Aug 23, 2012

  • Forum Post: RE: DLP4100 APPSFPGA 200MHz vs 400MHz

    Eyal Niv
    Thanks for the quick response. I am using the training pattern block from the TI example code.
    on Aug 23, 2012

  • Forum Post: RE: DLP4100 APPSFPGA 200MHz vs 400MHz

    Eyal Niv
    Hello Fizix, I am sorry it took me so long to respond. I've had a look today on the DAD2000 and am not sure how is it possible to measure the VBIAS rail without soldering a wire to the pin, which I rather not do. Can you describe in further details what would be the best way to probe the voltage...
    on Aug 30, 2012

  • Forum Post: DLP4100 APPSFPGA 200MHz vs 400MHz

    Eyal Niv
    Hello, I've been programming the APPSFPGA on the DLP4100 kit with my own algorithm leveraging the code supplied in TI's Extranet. My 200MHz design works fine, and the DMD mirror array work as expected. However, replacing the 200MHz PLL, with a 400MHz PLL (VHDL code also supplied by TI) produces...
    on Aug 9, 2012

  • Forum Post: DMD INTEGRATION WITH PHOTO DETECTOR.

    karthiraj s
    Hello, I am working with dmd d4100 explorer for implementation of single pixel camera.I am trying to focus an image on dmd. Also I am trying to focus the reflected image from dmd to a photo detector. So what is the photo detector i have to use, is there any specific part number for the photo detector...
    on Jan 16, 2013

  • Forum Post: Float command vs. PWR_FLOAT on Discovery 4100 chipset

    Jonathan Gauthier
    Hi, What is the main difference between float command send by BLKMD and BLKAD and there is a power float input pin? I've see that the example code does both send a float command and assert power float pin. It is mandatory to use both of them? The documentation says that "It is best...
    on Jan 31, 2013

  • Forum Post: RE: DLP4100 - Compiling the APPSFPGA code for the Discovery 4100 Explorer Software

    Robert T
    We just bought the D4100 and downloaded all of the available code from the extranet. NONE of the example FPGA code compiles... there aren't any ISE project files either. Has there been any progress on providing compilable VHDL code for the AppsFPGA?
    on Feb 26, 2013

All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.

Content on this site may contain or be subject to specific guidelines or limitations on use. All postings and use of the content on this site are subject to the Terms of Use of the site; third parties using this content agree to abide by any limitations or guidelines and to comply with the Terms of Use of this site. TI, its suppliers and providers of content reserve the right to make corrections, deletions, modifications, enhancements, improvements and other changes to the content and materials, its products, programs and services at any time or to move or discontinue any content, products, programs, or services without notice.

TI Worldwide | Contact Us | my.TI Login | Site Map | Corporate Citizenship | mobile m.ti.com (Mobile Version)

TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs and
embedded processors, along with software, tools and the industry’s largest sales/support staff.

© Copyright 1995-2013 Texas Instruments Incorporated. All rights reserved.
Trademarks | Privacy Policy | Terms of Use