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DLPC3430: Nature of LP connectivity

Stephen Craig
Intellectual 440 points
Part Number: DLPC3430
Other Parts Discussed in Thread: DLPC3435,

Hi,

For DSI interfaces in many FPGAs it is required to use four pins for each DSI lane in order to facilitate the Bidirectional Low Power mode. 

I know that the DLPC3435 doesn't support the Bidirectional, but I'm wondering about Low power.  The documentation for DLPC343x states that the DSI clock lane must be in a low power state upon deassertion of RESETZ, and must remain in that state for 100us after. 

My question is, does the DLPC3430  require the LP interface to be connected to any, all, or some subset of the lanes. 

I've included a diagram, which is an example of driving a MIPI DPHY with a Lattice FPGA.  In the top diagram (Figure 5) each lane is connect to 4 pins.  2 LVDS pins, and 2 LVCMOS pins, which facilitate the LP and Bidirectional functionality.  The bottom figure is high speed only, and only connects the 2 LVDS pins. 

  • 0
    TI__Mastermind 28005 points
    Stephen,

    I believe that, with the bottom setup, you will only be able to use HS interface. Adding the extra lines from the top setup will add LP support, but not bidirectional communication.

    I'll verify whether we have any documentation that indicates otherwise and, if so, I will let you know.

    Best Regards,
    Philippe Dollo
  • 0 in reply to Philippe Dollo
    Intellectual 440 points
    Hey Philippe,

    The documentation seems to indicate that DSI clock lanes requires this configuration because it has to maintain a Low Power state for 100us after reset.

    What I'm wondering is do the data lanes require the same Low Power functionality? If that is required, do all of the data lanes require it? For example, can we run a three lane setup with the clock and Lane 0 having a low power state, and Lane 1 and Lane 2 being high power only.

    The reason we ask is we are driving the MIPI lanes using an FPGA, and this would save us some IP pins.

    Thanks again for all the help, it is greatly appreciated.

    King Regards,
    Stephen Craig
  • 0 in reply to Stephen Craig
    TI__Mastermind 28005 points
    Stephen,

    I was able to talk to my team and, from experience, it does not appear that there has been a need to implement the LP functionality on the source side for our systems. I would, however, urge you to test yourself before implementing a full system as we did not formally test our system with a "simple" DSI circuit as your describe..

    I hope this helps.

    Best Regards,
    Philippe Dollo