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    Problem about Hardware Interrupt C5515

    This question is answered
    Ekrem Bayraktar
    Posted by Ekrem Bayraktar
    on Apr 25 2012 03:22 AM
    Expert1140 points

    Hi all,

    I have trouble to manage hardware interrupts on C5515, I am using EVM5515 with ADS1298 Board. I am trying to investigate the sample NON_Bios ECG project coming with ADS1298 board. There is an InterruptHandlers.c file taht manage interrupts in this project. Although I walk though the project and try to implement a similar code, I couldn't be able to successfully manage interrupt subroutine. I have also confusion about vectors.asm that determine the interrupt subroutines. As far as I understand there are some offsets for each ISR (I am using INT1 Hardware interrupt pin). Below is my vector.sm file view, in fact this is the file coming with evm5515_v1 folder downloaded from spectrum digital.

    *****************************************************************************
    * Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2008
    *
    * Use of this software is controlled by the terms and conditions found in the
    * license agreement under which this software has been supplied.
    *****************************************************************************
    ;Module: INTC
    ;File: vectors.asm - vector table
    ;**************************************************************************
    ;;**************************************************************************

    .C54CM_off
    .CPL_off
    .ARMS_off

    ;**********************************************************************************
    ; predefined stack operation modes
    ;**********************************************************************************
    ; USE_RETA : 2x16-bit fast return mode (RETA used)
    ; NO_RETA : 2x16-bit slow return mode (RETA not used)
    ; C54X_STK : 32-bit fast return mode

    ;**********************************************************************************
    .ref _c_int00
    ;.ref _sarISR
    .def RST

    ;**********************************************************************************
    .sect "vectors"
    .align 256
    .global _VECSTART
    ;**********************************************************************************
    _VECSTART:
    RST: .ivec reset_isr, USE_RETA ; Reset / Software Interrupt #0

    NMI: .ivec nmi_isr ; Nonmaskable Interrupt

    INT0: .ivec int0_isr ; External User Interrupt #0

    INT1: .ivec int1_isr ; External User Interrupt #1

    TINT: .ivec tim_isr ; Timer #0 / Software Interrupt #4

    PROG0: .ivec i2s0_mmc0_tx_isr ; Programmable 0 Interrupt

    UART: .ivec uart_isr ; IIS #1 Receive Interrupt

    PROG1: .ivec i2s0_mmc0_rx_isr ; Programmable 1 Interrupt

    DMA: .ivec dma_isr ; DMA Interrupt

    PROG2: .ivec i2s1_mmc1_tx_isr ; Programmable 2 Interrupt

    COPROCFFT: .ivec coprocfft_isr ; Coprocessor FFT Module Interrupt

    PROG3: .ivec i2s1_mmc1_rx_isr ; Programmable 3 Interrupt

    LCD: .ivec lcd_isr ; LCD Interrupt

    SARADC: .ivec saradc_isr ; SAR ADC Interrupt

    XMT2: .ivec i2s2_tx_isr ; I2S2 Tx Interrupt

    RCV2: .ivec i2s2_rx_isr ; I2S2 Rx Interrupt

    XMT3: .ivec i2s3_tx_isr ; I2S3 Tx Interrupt

    RCV3: .ivec i2s3_rx_isr ; I2S3 Rx Interrupt

    RTC: .ivec rtc_isr ; RTC interrupt

    SPI: .ivec spi_isr ; SPI Receive Interrupt

    USB: .ivec usb_isr ; USB Transmit Interrupt

    GPIO: .ivec gpio_isr ; GPIO Interrupt

    EMIF: .ivec emif_error_isr ; EMIF Error Interrupt

    I2C: .ivec i2c_isr ; IIC interrupt

    BERR: .ivec berr_isr ; Bus Error Interrupt

    DLOG: .ivec dlog_isr ; Emulation Interrupt - DLOG

    RTOS: .ivec rtos_isr ; Emulation Interrupt - RTOS

    RTDXRCV: .ivec rtdxrcv_isr ; Emulation Interrupt - RTDX receive

    RTDXXMT: .ivec rtdxxmt_isr ; Emulation Interrupt - RTDX transmit

    EMUINT: .ivec emuint_isr ; Emulation monitor mode interrupt

    SINT30: .ivec sint30_isr ; Software Interrupt #30

    SINT31: .ivec sint31_isr ; Software Interrupt #31

    .text
    reset_isr:
    ; *port(#0x1C01) = #0x0 ; Clear idles
    bit (ST1, #11) = #1 ; Disable interrupts
    @IVPD_L = #(RST >> 8) || mmap()
    @IVPH_L = #(RST >> 8) || mmap()
    bit(ST3,#7) = #0 ; Clear bus error interrupts

    @#IFR0_L = #0xFFFF || mmap() ; clear all pending interrupts
    @#IFR1_L = #0xFFFF || mmap()

    ;**********************************************************************************
    ; Reset all peripherals
    ;**********************************************************************************
    *port(#0x1C04) = 0x20
    nop_16
    *port(#0x1C05) = 0x00FF ; Reset all peripherals
    nop_16
    goto _c_int00


    nmi_isr: goto nmi_isr

    int0_isr: goto int0_isr

    int1_isr: goto int1_isr

    tim_isr: goto tim_isr

    i2s0_mmc0_tx_isr: goto i2s0_mmc0_tx_isr

    uart_isr: goto uart_isr

    i2s0_mmc0_rx_isr: goto i2s0_mmc0_rx_isr

    dma_isr: goto dma_isr

    i2s1_mmc1_tx_isr: goto i2s1_mmc1_tx_isr

    coprocfft_isr: goto coprocfft_isr

    i2s1_mmc1_rx_isr: goto i2s1_mmc1_rx_isr

    lcd_isr: goto lcd_isr

    saradc_isr: goto saradc_isr

    i2s2_tx_isr: goto i2s2_tx_isr

    i2s2_rx_isr: goto i2s2_rx_isr

    i2s3_tx_isr: goto i2s3_tx_isr

    i2s3_rx_isr: goto i2s3_rx_isr

    rtc_isr: goto rtc_isr

    spi_isr: goto spi_isr

    usb_isr: goto usb_isr

    gpio_isr: goto gpio_isr

    emif_error_isr: goto emif_error_isr

    i2c_isr: goto i2c_isr

    berr_isr:
    bit(ST3,#7) = #0 ; Clear bus error interrupts
    goto berr_isr

    dlog_isr: goto dlog_isr

    rtos_isr: goto rtos_isr

    rtdxrcv_isr: goto rtdxrcv_isr

    rtdxxmt_isr: goto rtdxxmt_isr

    emuint_isr: goto emuint_isr

    sint30_isr: goto sint30_isr

    sint31_isr: goto sint31_isr

    .text

    ********************************************************************************
    ** Name : no_isr **
    ** **
    ** Purpose : Spurious interrupt handler **
    ** **
    ** Author : **
    ** **
    ********************************************************************************
    no_isr: goto no_isr

    As far as I understand, I also need to define the starting adress of the vector table by setting IVPD and IVPH, which are also defined below:

    #define IVPD *( volatile Uint16* )(0x0049) // Interrupt vector pointer DSP
    #define IVPH *( volatile Uint16* )(0x004A) // Interrupt vector pointer HOST

    When I put some breakpoints inside my interrupt subroutine this breakpoints are not visited. When I enable IER0 - INT1 bit, the code begins to run forever. Below is my ISR just to try whether interrupt is working properly or not. I expect to take get a message on the console. I may not be able to print something to console inside interrupt therefore I try to read something from SPI registers like in the NONBIOS_ECG project but did not succeed at all.

    interrupt void int1_isr()
    {
    printf("\n Interrupt!");
    }

    Any comments, ideas, suggestions, resource recommendations are much appreciated.

    Thank you in advance.

    Regards.

    Ekrem.

    Interrupt C5515 EVM5515 HWI Hardware Interrupt
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    • Simon Attard
      Posted by Simon Attard
      on Apr 25 2012 07:37 AM
      Verified Answer
      Verified by Ekrem Bayraktar
      Intellectual730 points

      Hi,

      Again try to use the CSL to set up the ISR. Is is very easy to set up. The interrupt initialisation function should be something like this:

      void initialiseInterrupt(void)
      {
       
       IRQ_setVecs((Uint32)&VECSTART);
       IRQ_plug(INT1_EVENT,&intISR);
       IRQ_enable(INT1_EVENT);
       IRQ_globalEnable();
       
      }

      where intISR is interrupt service routine function.

      Are you sure that the data ready signal is actually happening? (i.e. that the pin is really being put to 0)

      Regards,

      Simon

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    • Ekrem Bayraktar
      Posted by Ekrem Bayraktar
      on Apr 25 2012 07:39 AM
      Expert1140 points

      To be more specific, I added the below code in order to illustrate what I do:

      #include <stdio.h>

      #define CPU_IER0_ADDR ((volatile unsigned*)0x0000)
      /**< CPU interrupt enable register0 address */
      #define CPU_IER1_ADDR ((volatile unsigned*)0x0045)
      /**< CPU interrupt enable register1 address */
      #define CPU_IFR0_ADDR ((volatile unsigned*)0x0001)
      /**< CPU interrupt flag register0 address */
      #define CPU_IFR1_ADDR ((volatile unsigned*)0x0046)
      /**< CPU interrupt flag register1 address */

      #define CPU_TIM0_CTRL ((ioport volatile unsigned*)0x1810)
      #define CPU_TIM0_PLWR ((ioport volatile unsigned*)0x1812)
      #define CPU_TIM0_PHWR ((ioport volatile unsigned*)0x1813)
      #define CPU_TIM0_CLWR ((ioport volatile unsigned*)0x1814)
      #define CPU_TIM0_CHWR ((ioport volatile unsigned*)0x1815)
      #define CPU_TIM0_IER ((ioport volatile unsigned*)0x1816)
      #define CPU_TIMINT_AGGR ((ioport volatile unsigned*)0x1c14)

      void setInterrupt()
      {
      asm("\tBIT (ST1, #ST1_INTM) = #0"); /*Enable GLobal Int.Mask*/

      /* Start the Timer0*/
      *CPU_TIM0_CTRL = *CPU_TIM0_CTRL | 0x0001;
      /*Enable INT1 interrupt */

      *CPU_IER0_ADDR = *CPU_IER0_ADDR | 0x0008;
      }

      interrupt void int1_isr()
      {
      printf("\n Interrupt!");
      }

      void Init()
      {
      *CPU_TIM0_CTRL = 0x8002;

      *CPU_TIM0_PLWR = 0x86A0;
      *CPU_TIM0_PHWR = 0x0001;

      *CPU_TIM0_CLWR = 0x0000;
      *CPU_TIM0_CHWR = 0x0000;

      *CPU_TIMINT_AGGR = 0x0000;
      }

      void main (void)
      {
      Init();
      printf("\n init complete");
      setInterrupt();
      }
      I also added the vector.asm file that I show above.
      Thank you for your help all.

      Ekrem.

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    • Ekrem Bayraktar
      Posted by Ekrem Bayraktar
      on Apr 25 2012 08:10 AM
      Expert1140 points

      Simon Attard

      Hi,

      Again try to use the CSL to set up the ISR. Is is very easy to set up. The interrupt initialisation function should be something like this:

      void initialiseInterrupt(void)
      {
       
       IRQ_setVecs((Uint32)&VECSTART);
       IRQ_plug(INT1_EVENT,&intISR);
       IRQ_enable(INT1_EVENT);
       IRQ_globalEnable();
       
      }

      where intISR is interrupt service routine function.

      Are you sure that the data ready signal is actually happening? (i.e. that the pin is really being put to 0)

      Regards,

      Simon

      Woow thank you Simon,

      Finally I got the point, appreciate it.

      Regards.

      Ekrem.

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    • Ekrem Bayraktar
      Posted by Ekrem Bayraktar
      on Apr 25 2012 08:55 AM
      Expert1140 points

      Hi Simon,

      Do you have any idea about the below statement (taken from CSL API reference Guide). Because I want to use HWI in my design.

      IRQ_plug() is the only API function that cannot be used when DSP/BIOS
      dispatcher is present or DSP/BIOS HWI module is used to configure the
      interrupt vectors. This function, IRQ_plug(), dynamically places code at the
      interrupt vector location to branch to a user-defined ISR for a specified event.
      If you call IRQ_plug() when DSP/BIOS dispatcher is present or HWI module
      has been used to configure interrupt vectors, this could disrupt the DSP/BIOS
      operating environment.
      Regards.

      Ekrem.

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    • Simon Attard
      Posted by Simon Attard
      on Apr 25 2012 15:32 PM
      Intellectual730 points

      Hi EkremBayraktar,

      Basically what that statement means is that you cannot use IRQ_plug() if you are using DSP/BIOS. There are examples in the CSL documentation on how you have to initialise the interrupts if you are using DSP/BIOS.

      The reason why you cannot use that function is because it writes to the IVT dynamically (on the run). This could interfere with the DSP/BIOS setup and scheduling.

      To be honest I do not have any experience with DSP/BIOS so I cannot offer further help on that.

      Regards,

      Simon

       

      Don't forget to verify any answers! :)

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