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Clock managing

Dear Mr/Ms

We use C5504 - 150 MHz. According to SPRS659D Table 6.3 it should be used CLKIN for achivment 150 MHz. But our device includes other chip that requirs 32.768 kHz clock.

  1. Therefore DSP is started with pin CLK_SEL=0 and pin CLK_IN=0 and boot is performed.  RTCCLKOUT is enabled.  
  2. PLL is bypassed and reprogrammed  to 150 MHz at CLKIN= 12 MHz
  3. External frequency 12 MHz is connected to CLKIN
  4. CLK_IN is switched to High.
  5. PLLBYPASS is disabled.

I have any questions:

  1. Is it possible the scenario above?
  2. Does RTCCLKOUT continue after switching to CLKIN or closed?
  3. May be used diferent frequency (not 12 MHz) as CLKIN in this scenario.

Thanks

Sergey Zevelev

 

1 Reply

  • Hello Sergey,

    Correct me if I guess wrong, in between step 1 and 2, you will be dynamically switching CLK_SEL from 0 to 1 in order to use CLKIN as clock source. CLK_SEL is not allowed to change during device operation. It must be tied high or low at the board.

    • Therefore DSP is started with pin CLK_SEL=0 and pin CLK_IN=0 and boot is performed.  RTCCLKOUT is enabled.  
    • PLL is bypassed and reprogrammed  to 150 MHz at CLKIN= 12 MHz

    regards.