I moved your thread here to the C5000 forum to hopefully get you in touch with some more C5000 specific experts. As to the question at hand I believe the better part of your answer can be found in section 4.3.6 of the datasheet. It looks like there is a prioritization scheme available with the ILR register, and that it should submit subsequent interrupts in priority order as each ISR completes and writes a 1 to the NEW_IRQ_AGR bit. I imagine you could lose interrupt events if the same event happened so quickly that the first event was not given time to be serviced and cleared, though seperate events appear to be handled properly with priority even if two were to happen simultaneously. Hopefully someone more familiar with this device can clarify, as I do not do much work with these parts.