LOW POWER ABOUT 5510

Hello,everyone.I have a problem about 5510's LOW POWER.

Acorrding to the datasheet,there are six idle domains.The DSP will be in idle mode if we write 1 into the bits and the lowest current is 1mA.

NOW the question is that I write 1 to the fifth to zero bit of the ICR,but I get 70mA.

By the way, there is a bit of IDLEEN in Mcbsp's and timer's register and I also set it 1.the result is 70mA.

I have no idea whether or not my source is correct. Please help me if you have done this or understand it .

much more appreciated,if offer the source.

thank you. 

8 Replies

  • If you put the SDRAM in a self-refresh state you can then idle the EMIF.  More documentation on this subject can be found in section 3.9.3.2 of the EMIF Reference Guide.

    If you have an emulator connected to your board then you will not be able to idle the CPU.

    Make sure that no interrupts are pending in IFR0/IFR1 when you try to idle the CPU.  You can clear pending interrupts by writing 0xFFFF to IFR0/IFR1.

    Also, check out this article:

    http://eetimes.com/news/latest/showArticle.jhtml?articleID=187201644

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    http://processors.wiki.ti.com/index.php/User:BradGriffis
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  • In reply to Brad Griffis:

    Hi
    I think I have a similar problem, but how can i set the IFR0/IFR1? there is no function or macro in the CSL to do that... is there an instruction or example code you can provide?
    best regards
    aziz
  • In reply to aziz shammas:

    Looking at the 5510A data manual, the register addresses are given in Table 3−9 "CPU Registers". IFR0 is at word address 0x01 and IFR1 is at word address 0x46. You can access them by creating a simple definition such as this:

    #define IFR0 (*(volatile unsigned short int*)0x000001)
    #define IFR1 (*(volatile unsigned short int*)0x000046)

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    http://processors.wiki.ti.com/index.php/User:BradGriffis
    --------------------------------------------------------------------------------------------------------- 

  • In reply to Brad Griffis:

    hi brad

    I'm a bit new to the domain, so I'm having trouble doing this right...

    I assume that we are defining an address pointer named IFR0 (and IFR1), and we should load this address by 0xffff, to do that i used this instruction:

    * IFR0 = 0xFFFF;

    it returns an error.

    so could you please point out what I'm doing wrong?

    and if you can provide an example code...

    I appreciate your help

    best regards

    aziz

  • In reply to aziz shammas:

    I already dereferenced the pointer in the definition:

    #define IFR0 (*(volatile unsigned short int*)0x000001)

    So you would do

    IFR0 = 0xFFFF;

    ---------------------------------------------------------------------------------------------------------
    http://processors.wiki.ti.com/index.php/User:BradGriffis
    --------------------------------------------------------------------------------------------------------- 

  • In reply to Brad Griffis:

    hi brad
    I've figured it out just few moments ago, but thank you for the reply...
    if I may i have a question:
    I'm trying to IDLE my 5510 CPU... I found a training document that stated that I should do the following:
    1- add powerDown routine in my main code
    2- choose IDLE power down options in GUI (power configuration manager)
    3- create IDLE thread for powerDown function (using GUI as well)

    I did all the steps exactly as mentioned in the document, on a simple audio app (sound in sound out using SWI...) but when I burn the file to the flash and run, the CPU seems freezing and the sound coming out is like a woodpecker.

    this happens only when I choose to idle CPU in power configuration manager (GUI)...

    is there an explanation why is this happining?
    is there any thing I'm missing?
    best regards
    aziz
  • In reply to aziz shammas:

    aziz shammas
    I did all the steps exactly as mentioned in the document, on a simple audio app (sound in sound out using SWI...) but when I burn the file to the flash and run, the CPU seems freezing and the sound coming out is like a woodpecker.

    The dreaded woodpecker!  I've encountered that many times.  :-)

    That's due to the DMA sending the same buffer(s) over and over (i.e. the CPU is not updating the buffer contents).  Sounds like perhaps you don't have the interrupt bit masks configured correctly for the CPU to wake back up and continue handling interrupts.

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    http://processors.wiki.ti.com/index.php/User:BradGriffis
    --------------------------------------------------------------------------------------------------------- 

  • In reply to Brad Griffis:

    the CPU should be interrupted when the DMA completes a full buffer, i assumed that this should be enough to wake it up, shouldn't it?
    do you have any suggestions?
    this is a copy of my code adding the power down routine

    //include//

    #include "icom_5510cfg.h"
    #include "dsk5510.h"
    #include "dsk5510_aic23.h"
    #include "dsk5510_dip.h"
    #include "dsk5510_led.h"

    #include <csl.h>
    #include <csl_dma.h>
    #include <csl_irq.h>
    #include <csl_gpio.h>
    #include <csl_timer.h>
    #include <csl_pwr.h>

    #include<std.h>
    #include<hwi.h>
    #include<swi.h>
    #include<log.h>

    //prototypes//
    void initDma (void);
    void initIrq (void);
    void dmaHwi (void);
    void initMcBSP (void);
    void processBuffer (void);
    void copyData (short *inbuf, short *outbuf ,int length);
    void powerDown (void);

    //declaration//

    #define BUFFSIZE 1024
    #define PING 0
    #define PONG 1
    #define IFR0 (volatile unsigned short int*)0x000001
    #define IFR1 (volatile unsigned short int*)0x000046

    //global variables//

    short gBufferRcvPingL[BUFFSIZE/2];
    short gBufferRcvPingR[BUFFSIZE/2];
    short gBufferRcvPongL[BUFFSIZE/2];
    short gBufferRcvPongR[BUFFSIZE/2];
    short gBufferXmtPingL[BUFFSIZE/2];
    short gBufferXmtPingR[BUFFSIZE/2];
    short gBufferXmtPongL[BUFFSIZE/2];
    short gBufferXmtPongR[BUFFSIZE/2];

    int pingOrPong=PING;
    Uint16 eventId;
    Uint16 inter0Id;
    Uint16 inter1Id;
    Uint16 addr;
    int x=0;

    DMA_Handle hDmaXmt;
    DMA_Handle hDmaRcv;
    DSK5510_AIC23_CodecHandle hCodec;
    MCBSP_Handle C55XX_CONTROLHANDLE_hMcbsp;
    MCBSP_Handle C55XX_DMA_MCBSP_hMcbsp;

    DMA_Config gDmaConfigXmt = {
    DMA_DMACSDP_RMK(
    DMA_DMACSDP_DSTBEN_NOBURST,
    DMA_DMACSDP_DSTPACK_OFF,
    DMA_DMACSDP_DST_PERIPH,
    DMA_DMACSDP_SRCBEN_NOBURST,
    DMA_DMACSDP_SRCPACK_OFF,
    DMA_DMACSDP_SRC_DARAM,
    DMA_DMACSDP_DATATYPE_16BIT
    ), /* Source/Destination Register - DMACSDP */
    DMA_DMACCR_RMK(
    DMA_DMACCR_DSTAMODE_CONST,
    DMA_DMACCR_SRCAMODE_DBLINDX,
    DMA_DMACCR_ENDPROG_OFF,
    DMA_DMACCR_REPEAT_ALWAYS,
    DMA_DMACCR_AUTOINIT_ON,
    DMA_DMACCR_EN_STOP,
    DMA_DMACCR_PRIO_HI,
    DMA_DMACCR_FS_DISABLE,
    DMA_DMACCR_SYNC_XEVT2
    ), /* Control Register - DMACCR */
    DMA_DMACICR_RMK(
    DMA_DMACICR_BLOCKIE_OFF,
    DMA_DMACICR_LASTIE_OFF,
    DMA_DMACICR_FRAMEIE_OFF,
    DMA_DMACICR_FIRSTHALFIE_OFF,
    DMA_DMACICR_DROPIE_OFF,
    DMA_DMACICR_TIMEOUTIE_OFF
    ), /* Interrupt Control Register - DMACICR */
    0, /* Lower Source Address - DMACSSAL */
    0, /* Upper Source Address - DMACSSAU */
    0, /* Lower Destination Address - DMACDSAL */
    0, /* Upper Destination Address - DMACDSAU */
    2, /* Element Number - DMACEN */
    BUFFSIZE/2, /* Frame Number - DMACFN */
    65536-(BUFFSIZE-1), /* Frame Index - DMACFI */
    BUFFSIZE-1 /* Element Index - DMACEI */
    };

    DMA_Config gDmaConfigRcv = {
    DMA_DMACSDP_RMK(
    DMA_DMACSDP_DSTBEN_NOBURST,
    DMA_DMACSDP_DSTPACK_OFF,
    DMA_DMACSDP_DST_DARAM,
    DMA_DMACSDP_SRCBEN_NOBURST,
    DMA_DMACSDP_SRCPACK_OFF,
    DMA_DMACSDP_SRC_PERIPH,
    DMA_DMACSDP_DATATYPE_16BIT
    ), /* Source/Destination Register - DMACSDP */
    DMA_DMACCR_RMK(
    DMA_DMACCR_DSTAMODE_DBLINDX,
    DMA_DMACCR_SRCAMODE_CONST,
    DMA_DMACCR_ENDPROG_OFF,
    DMA_DMACCR_REPEAT_ALWAYS,
    DMA_DMACCR_AUTOINIT_ON,
    DMA_DMACCR_EN_STOP,
    DMA_DMACCR_PRIO_HI,
    DMA_DMACCR_FS_DISABLE,
    DMA_DMACCR_SYNC_REVT2
    ), /* Control Register - DMACCR */
    DMA_DMACICR_RMK(
    DMA_DMACICR_BLOCKIE_ON,
    DMA_DMACICR_LASTIE_OFF,
    DMA_DMACICR_FRAMEIE_OFF,
    DMA_DMACICR_FIRSTHALFIE_OFF,
    DMA_DMACICR_DROPIE_OFF,
    DMA_DMACICR_TIMEOUTIE_OFF
    ), /* Interrupt Control Register - DMACICR */
    0, /* Lower Source Address - DMACSSAL */
    0, /* Upper Source Address - DMACSSAU */
    0, /* Lower Destination Address - DMACDSAL */
    0, /* Upper Destination Address - DMACDSAU */
    2, /* Element Number - DMACEN */
    BUFFSIZE/2, /* Frame Number - DMACFN */
    65536-(BUFFSIZE-1), /* Frame Index - DMACFI */
    BUFFSIZE-1 /* Element Index - DMACEI */
    };
    DSK5510_AIC23_Config config = { \
    0x0017, /* 0 DSK5510_AIC23_LEFTINVOL Left line input channel volume */
    0x0017, /* 1 DSK5510_AIC23_RIGHTINVOL Right line input channel volume */
    0x01f9, /* 2 DSK5510_AIC23_LEFTHPVOL Left channel headphone volume */
    0x01f9, /* 3 DSK5510_AIC23_RIGHTHPVOL Right channel headphone volume */
    0x0010, /* 4 DSK5510_AIC23_ANAPATH Analog audio path control */
    0x0000, /* 5 DSK5510_AIC23_DIGPATH Digital audio path control */
    0x0000, /* 6 DSK5510_AIC23_POWERDOWN Power down control */
    0x0043, /* 7 DSK5510_AIC23_DIGIF Digital audio interface format */
    0x008d, /* 8 DSK5510_AIC23_SAMPLERATE Sample rate control */
    0x0001 /* 9 DSK5510_AIC23_DIGACT Digital interface activation */
    };

    MCBSP_Config mcbspCfg1 = {
    0x1000, /* Serial Port Control Register 1 */
    0x0100, /* Serial Port Control Register 2 */
    0x0000, /* Receive Control Register 1 */
    0x0000, /* Receive Control Register 2 */
    0x0040, /* Transmit Control Register 1 */
    0x0000, /* Transmit Control Register 2 */
    0x0063, /* Sample Rate Generator Register 1 */
    0x2013, /* Sample Rate Generator Register 2 */
    0x0000, /* Multichannel Control Register 1 */
    0x0000, /* Multichannel Control Register 2 */
    0x1a0a, /* Pin Control Register */
    0x0000, /* Receive Channel Enable Register Partition A */
    0x0000, /* Receive Channel Enable Register Partition B */
    0x0000, /* Receive Channel Enable Register Partition C */
    0x0000, /* Receive Channel Enable Register Partition D */
    0x0000, /* Receive Channel Enable Register Partition E */
    0x0000, /* Receive Channel Enable Register Partition F */
    0x0000, /* Receive Channel Enable Register Partition G */
    0x0000, /* Receive Channel Enable Register Partition H */
    0x0000, /* Transmit Channel Enable Register Partition A */
    0x0000, /* Transmit Channel Enable Register Partition B */
    0x0000, /* Transmit Channel Enable Register Partition C */
    0x0000, /* Transmit Channel Enable Register Partition D */
    0x0000, /* Transmit Channel Enable Register Partition E */
    0x0000, /* Transmit Channel Enable Register Partition F */
    0x0000, /* Transmit Channel Enable Register Partition G */
    0x0000 /* Transmit Channel Enable Register Partition H */
    };

    MCBSP_Config mcbspCfg2 = {
    0x0000, /* Serial Port Control Register 1 */
    0x0100, /* Serial Port Control Register 2 */
    0x0140, /* Receive Control Register 1 */
    0x0000, /* Receive Control Register 2 */
    0x0140, /* Transmit Control Register 1 */
    0x0000, /* Transmit Control Register 2 */
    0x0000, /* Sample Rate Generator Register 1 */
    0x0000, /* Sample Rate Generator Register 2 */
    0x0000, /* Multichannel Control Register 1 */
    0x0000, /* Multichannel Control Register 2 */
    0x0003, /* Pin Control Register */
    0x0000, /* Receive Channel Enable Register Partition A */
    0x0000, /* Receive Channel Enable Register Partition B */
    0x0000, /* Receive Channel Enable Register Partition C */
    0x0000, /* Receive Channel Enable Register Partition D */
    0x0000, /* Receive Channel Enable Register Partition E */
    0x0000, /* Receive Channel Enable Register Partition F */
    0x0000, /* Receive Channel Enable Register Partition G */
    0x0000, /* Receive Channel Enable Register Partition H */
    0x0000, /* Transmit Channel Enable Register Partition A */
    0x0000, /* Transmit Channel Enable Register Partition B */
    0x0000, /* Transmit Channel Enable Register Partition C */
    0x0000, /* Transmit Channel Enable Register Partition D */
    0x0000, /* Transmit Channel Enable Register Partition E */
    0x0000, /* Transmit Channel Enable Register Partition F */
    0x0000, /* Transmit Channel Enable Register Partition G */
    0x0000 /* Transmit Channel Enable Register Partition H */
    };

    //main//

    void main (void){

    DSK5510_init();
    DSK5510_LED_init();

    initDma(); //call DMA initialization function
    initIrq(); //call interrupt request initialization function
    initMcBSP();

    hCodec = DSK5510_AIC23_openCodec(0, &config);

    //MCBSP_start(C55XX_DMA_MCBSP_hMcbsp,0xf,0xDC);
    DMA_RGETH(hDmaRcv,DMACSR); //read the DMA status registers to allow next interrupt
    DMA_start(hDmaRcv);
    DMA_start(hDmaXmt);


    MCBSP_FSET (PCR2 , IDLEEN , 1);


    // Now that the DMA config regs have been transferred to the working
    // regs we need to reprogram the rcv dst and xmt src config regs
    addr = ((Uint32)gBufferRcvPongL) << 1;
    DMA_RSETH(hDmaRcv, DMACDSAL, addr & 0xffff);
    DMA_RSETH(hDmaRcv, DMACDSAU, (addr >> 16) & 0xffff);

    addr = ((Uint32)gBufferXmtPongL) << 1;
    DMA_RSETH(hDmaXmt, DMACSSAL, addr & 0xffff);
    DMA_RSETH(hDmaXmt, DMACSSAU, (addr >> 16) & 0xffff);
    }

    //helping functions

    void processBuffer (void){
    short PingPong;
    PingPong=SWI_getmbox();

    DSK5510_LED_toggle(0);

    if (PingPong==PING){
    DSK5510_LED_toggle(1);
    copyData(gBufferRcvPingL,gBufferXmtPingL,BUFFSIZE);

    // Reprogram config regs for PingL
    addr = ((Uint32)gBufferRcvPingL) << 1;
    DMA_RSETH(hDmaRcv, DMACDSAL, addr & 0xffff);
    DMA_RSETH(hDmaRcv, DMACDSAU, (addr >> 16) & 0xffff);

    addr = ((Uint32)gBufferXmtPingL) << 1;
    DMA_RSETH(hDmaXmt, DMACSSAL, addr & 0xffff);
    DMA_RSETH(hDmaXmt, DMACSSAU, (addr >> 16) & 0xffff);

    }

    else{
    DSK5510_LED_toggle(2);
    copyData(gBufferRcvPongL,gBufferXmtPongL,BUFFSIZE);

    // Reprogram config regs for PongL
    addr = ((Uint32)gBufferRcvPongL) << 1;
    DMA_RSETH(hDmaRcv, DMACDSAL, addr & 0xffff);
    DMA_RSETH(hDmaRcv, DMACDSAU, (addr >> 16) & 0xffff);

    addr = ((Uint32)gBufferXmtPongL) << 1;
    DMA_RSETH(hDmaXmt, DMACSSAL, addr & 0xffff);
    DMA_RSETH(hDmaXmt, DMACSSAU, (addr >> 16) & 0xffff);
    }
    powerDown ();
    }

    void initDma (void){
    hDmaXmt=DMA_open(DMA_CHA_ANY,DMA_OPEN_RESET);
    hDmaRcv=DMA_open(DMA_CHA_ANY,DMA_OPEN_RESET);

    gDmaConfigXmt.dmacssal=(DMA_AdrPtr)(((Uint32)(&gBufferXmtPingL)<<1)&0x00FFFF);
    gDmaConfigXmt.dmacssau=(Uint16)((((Uint32)(&gBufferXmtPingL)<<1)&0xFF000)>>16);
    gDmaConfigXmt.dmacdsal=(DMA_AdrPtr)(((Uint32)(&_MCBSP_DXR12)<<1)&0x00FFFF);
    gDmaConfigXmt.dmacdsau=(Uint16)((((Uint32)(&_MCBSP_DXR12)<<1)&0x00FFFF)>>16);

    gDmaConfigRcv.dmacssal=(DMA_AdrPtr)(((Uint32)(&_MCBSP_DRR12)<<1)&0x00FFFF);
    gDmaConfigRcv.dmacssau=(Uint16)((((Uint32)(&_MCBSP_DRR12)<<1)&0xFF000)>>16);
    gDmaConfigRcv.dmacdsal=(DMA_AdrPtr)(((Uint32)(&gBufferRcvPingL)<<1)&0x00FFFF);
    gDmaConfigRcv.dmacdsau=(Uint16)((((Uint32)(&gBufferRcvPingL)<<1)&0x00FFFF)>>16);

    DMA_config(hDmaXmt, &gDmaConfigXmt);
    DMA_config(hDmaRcv, &gDmaConfigRcv);
    }



    void initIrq (void){
    eventId = DMA_getEventId(hDmaRcv); //get event Id from DMA interrupt
    inter0Id = IRQ_EVT_INT0;
    inter1Id = IRQ_EVT_INT1;

    IRQ_clear(eventId);
    IRQ_clear(inter0Id);
    IRQ_clear(inter1Id);

    IRQ_enable(eventId);
    IRQ_enable(inter0Id);
    IRQ_enable(inter1Id);

    //IRQ_plug(eventId, &dmaHwi);
    HWI_dispatchPlug(eventId,(Fxn)dmaHwi, NULL);
    HWI_dispatchPlug(inter0Id,(Fxn)ext0Hwi, NULL);
    HWI_dispatchPlug(inter1Id,(Fxn)ext1Hwi, NULL);

    IRQ_globalEnable();
    }


    void dmaHwi(void)
    {
    DMA_RGETH(hDmaRcv, DMACSR);
    if(pingOrPong==PING){
    SWI_or(&processBufferSwi,PING);
    pingOrPong=PONG;
    }
    else{
    SWI_or(&processBufferSwi,PONG);
    pingOrPong=PING;
    }
    }


    void initMcBSP (void){
    C55XX_CONTROLHANDLE_hMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
    C55XX_DMA_MCBSP_hMcbsp = MCBSP_open(MCBSP_PORT2, MCBSP_OPEN_RESET);
    MCBSP_config(C55XX_CONTROLHANDLE_hMcbsp, &mcbspCfg1);
    MCBSP_config(C55XX_DMA_MCBSP_hMcbsp, &mcbspCfg2);
    }


    void copyData(short *inbuf, short *outbuf ,int length )
    {
    int i = 0;
    for (i = 0; i < length; i++)
    {
    outbuf[i] = inbuf[i]
    }
    }


    void powerDown (void)
    {
    PWR_FSET (ICR , PERI , 1);
    PWR_FSET (ICR , CPUI , 1);
    PWR_FSET (ICR , CLKGENI , 1);
    * IFR0 = 0xFFFF;
    * IFR1 = 0xFFFF;
    PWR_powerDown(PWR_WAKEUP_MI);
    DSK5510_LED_toggle(3);
    return;
    }

    any comments?
    best regards
    Aziz