FIR filter implementation in C55xx processor

This processor will support 400 coefficients, provided it has enough CPU cycles to keep up.  What sample rate?

Aravind,

Well, using fir2() you could execute n_firs FIR operations per second:

n_firs = cpu / (nx * (3 + nh/2) + 25)

where:

cpu = clock rate, Hz

nx = buffer size

nh = n coefficients

So, for cpu=120e6, nx=1024, nh=400, I get n_firs of 577.  So, theoretically for four channels you could execute a 400 point FIR on every sample at 147.7 kHz.  In reality, though, the processor has other things to do also.

Hope this helps,

Bill

Hi Sir,

Thanks for your reply. I shared it with customer, they are ok with it. I am having one more doubt, in the datasheet it is mentioned this DSP is having 320KB on-chip memory. Is it a flash? If it is flash can we implement complete program on it?

Does this DSP needs any external flash compulsory

Below is the exact query from customer which i typed from their email content

"Hi,

      Ok For me.  Is it possible to run the All the Code (FIR Filter Functionality only)  inside the Flash?  Or its require External Flash Compulsory."

Kindly need your valuable reply

Regards,

Aravind

Aravind,

The 320KB is static RAM.  Some external non-volatile program storage is required.  The datasheet describes what technologies the built-in bootloader supports.

Bill

Hi Sir,

Thanks for your reply. Ok now i came to know that this DSP can be used for filtering and can implement 400 coefficients, but the thing is it needs eternal flash for programming

Regards,

Aravind.