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McBSP TMS5416 in SPI mode

Other Parts Discussed in Thread: TMS320VC5416

Dear Sir/Madam,
We are using TMS320VC5416 processor. We wanted to use McBSP in clock stop mode for some SPI application.
Details are as follows,
Processor: Master
SPI mode: 3 (both clock phase and clock polarity are one. CLKXP = 1b; CLKSTP = 10b)
No of words per frame: 3 words, each word consisting of 8 bits of data.

We are facing some issue. When want to transfer the 3 words (each of 8 bits) data is coming properly but clock is not coming properly. Clock is coming like 8 bits, 9 bits and 9 bits. (Please see the attachment)

Can you kindly send the proper settings???
My register configurations are as follows,

#define McBSP_SRGR10      0x00A0
#define McBSP_SRGR20      0x2000 

#define McBSP_PCR0          0x0F0E
#define McBSP_SPCR10      0x10a0
#define McBSP_SPCR20      0x0240 

#define McBSP_RCR10       0x0200
#define McBSP_RCR20       0x0200
#define McBSP_XCR10       0x0200
#define McBSP_XCR20        0x0200 .



Thank you,

  • Hello Aravind,

     Your configurations looks correct, I could not view your attachment ( I am not sure whether you had attached the scope snapshots)

    But as mentioned in the TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals :  section 2.3.1  -  As a initialization procedure, Sample rate generator  Wait for two bit clocks. This is to ensure proper synchronization internally.

    Below are the details:

    After device reset is complete (RS = 1), the serial port initialization procedure is as follows:

    1) Set XRST = RRST = FRST = 0 in SPCR[1,2]. If coming out of device reset, this step is not required.

    2) Program only the McBSP configuration registers (and not the data registers) listed in Table 2−2, McBSP Registers , on page 2-5, as required when the serial port is in reset state (XRST = RRST = FRST = 0).

    3) Wait for two bit clocks. This is to ensure proper synchronization internally.

    4) Set up data acquisition as required such as writing to DXR.

    5) Set XRST = RRST= 1 to enable the serial port. Note that the value written to SPCR[1,2] at this time should have only the reset bits changed to 1, and the remaining bit-fields should have the same value as in step 2 above.

    Hope the above information helps.

    Regards

     Vasanth

     

  • Dear Vasant,

    Thank you very much for replying.

    Yes, I am waiting 80 clock cycles (12.5 nano seconds * 80 cycles).

    I have tried writing 8 bit, 8 bit & 8 bit to the DXR1 register. Still there is no improvement.
     (please see the below code)

        *SPSA_CH2 = SPCR2_CH2_ADDR;
        while (!(Tx_Ready_Chk = *SPSD_CH2 & 0x0002));
        *DXR1_CH2 = (short) CmdWrd;
         
         SPSA_CH2 = SPCR2_CH2_ADDR;
        while (!(Tx_Ready_Chk = *SPSD_CH2 & 0x0002));
         *DXR1_CH2 = (short) RegAddr;
         
         *SPSA_CH2 = SPCR2_CH2_ADDR;
        while (!(Tx_Ready_Chk = *SPSD_CH2 & 0x0002));
         *DXR1_CH2 = (short) RegValue;

    It is correct way right?? I have initialized, 8 bits per word and 3 words per frame.

    Please see my new configuration,

     

       *SPSA_CH2 = SPCR1_CH2_ADDR;
        *SPSD_CH2 = 0x0000;
        
        *SPSA_CH2 = SPCR2_CH2_ADDR;
        *SPSD_CH2 = 0x0000;
        
        *SPSA_CH2 = SPCR1_CH2_ADDR;
        *SPSD_CH2 = 0x1000;
        
        *SPSA_CH2 = SPCR2_CH2_ADDR;
        *SPSD_CH2 = 0x0000;
        
        *SPSA_CH2 = PCR_CH2_ADDR;
        *SPSD_CH2 = 0x0A0A;
        
        *SPSA_CH2 = XCR1_CH2_ADDR;
        *SPSD_CH2 = 0x0200;
        
        *SPSA_CH2 = RCR1_CH2_ADDR;
        *SPSD_CH2 = 0x0200;
        
        *SPSA_CH2 = XCR2_CH2_ADDR;
        *SPSD_CH2 = 0x0001;
        
        *SPSA_CH2 = RCR2_CH2_ADDR;
        *SPSD_CH2 = 0x0001;
        
        *SPSA_CH2 = SRGR2_CH2_ADDR;
        *SPSD_CH2 = 0x2000;
        
        *SPSA_CH2 = SRGR1_CH2_ADDR;
        *SPSD_CH2 = 0x00C7;
        
        *SPSA_CH2 = SPCR2_CH2_ADDR;
        *SPSD_CH2 = *SPSD_CH2 | 0x0040;
        
        SPI_Delay(90);
        SPIReadWriteEn();
        SPI_Delay(90);


    Please find the attachment for the snapshot.

    Thank You very much for helping!!

  • Hello Aravind,

    In PCR register can you change your CLKRP setting, for the receiver to sample on the rising edge instead of falling edge.

    Please let me know what you see once you change to this setting.

    Regards

     Vasanth

     

  • Dear Vasanth,

    Yes, I changed CLKRP setting as you told. But still there is no improvement. (you can see the attached snap-shot).

    I have inserted 5 cycles of clock delay after every register configuration. I tried in this way too.. but still there is no improvement.

    void SPI_Ch2_Init (void)
    {
    	VUINT16 SPCR1,SPCR2,PCR,RCR1,RCR2,XCR1, XCR2,SRGR1,SRGR2;
    		
    	SPSA_CH2 = (VUINT16 *) SPSA_CH2_ADDR;
    	SPSD_CH2 = (VUINT16 *) SPSD_CH2_ADDR;
    	SPI_Delay(5);
    	*SPSA_CH2 = SPCR1_CH2_ADDR;
    	*SPSD_CH2 = 0x0000;
    	SPI_Delay(5);
    	*SPSA_CH2 = SPCR2_CH2_ADDR;
    	*SPSD_CH2 = 0x0000;
    	SPI_Delay(5);
    	*SPSA_CH2 = SPCR1_CH2_ADDR;
    	*SPSD_CH2 = 0x1000;
    	SPI_Delay(5);
    	*SPSA_CH2 = SPCR2_CH2_ADDR;
    	*SPSD_CH2 = 0x0000;
    	SPI_Delay(5);
    	*SPSA_CH2 = PCR_CH2_ADDR;
    	*SPSD_CH2 = 0x0A0B;
    	SPI_Delay(5);
    	*SPSA_CH2 = XCR1_CH2_ADDR;
    	*SPSD_CH2 = 0x0200;
    	SPI_Delay(5);
    	*SPSA_CH2 = RCR1_CH2_ADDR;
    	*SPSD_CH2 = 0x0200;
    	SPI_Delay(5);
    	*SPSA_CH2 = XCR2_CH2_ADDR;
    	*SPSD_CH2 = 0x0001;
    	SPI_Delay(5);
    	*SPSA_CH2 = RCR2_CH2_ADDR;
    	*SPSD_CH2 = 0x0001;
    	SPI_Delay(5);
    	*SPSA_CH2 = SRGR2_CH2_ADDR;
    	*SPSD_CH2 = 0x2000;
    	SPI_Delay(5);
    	*SPSA_CH2 = SRGR1_CH2_ADDR;
    	*SPSD_CH2 = 0x00C7;
    	
    	SPI_Delay(5);
    	
    	*SPSA_CH2 = SPCR2_CH2_ADDR;
    	*SPSD_CH2 = *SPSD_CH2 | 0x0040;
    	
    	SPI_Delay(90);
    	SPIReadWriteEn();
    	SPI_Delay(90);
    }

    I am wring to DXR in this way...

    	DXR1_CH2 = (VUINT16 *) DXR1_CH2_ADDR;
    	DXR2_CH2 = (VUINT16 *) DXR2_CH2_ADDR;
    	DRR1_CH2 = (VUINT16 *) DRR1_CH2_ADDR;
    	DRR2_CH2 = (VUINT16 *) DRR2_CH2_ADDR;
    
     	SPI_Delay(50);
     	
    	*SPSA_CH2 = SPCR2_CH2_ADDR;
    	while (!(Tx_Ready_Chk = *SPSD_CH2 & 0x0002));
    	*DXR1_CH2 = (short) 0xF0;
    	
    	
    	*SPSA_CH2 = SPCR2_CH2_ADDR;
    	while (!(Tx_Ready_Chk = *SPSD_CH2 & 0x0002));
    	*DXR1_CH2 = (short) 0xF0;
    	
    	
    	*SPSA_CH2 = SPCR2_CH2_ADDR;
    	while (!(Tx_Ready_Chk = *SPSD_CH2 & 0x0002));
    	*DXR1_CH2 = (short) 0xF0;

    Is this the proper way to write the to SPI DX????? Anything is wrong here??

    Thank you for the support.

    Regards,

    Aravind D Chakravarti

  • Dear Vasanth,

    Shall I send you the entire code???

    Regards,

    Aravind D Chakravarti,

    System Engineer,

    Accord Software and Systems Pvt. Ltd.,

    Bangalore

  • Hello Aravind,

       Suggest you to try on the below mentioned points

      1. Set word per frame to be one instead of three, but do send multiple  frames and see whether you still observe the same clock behavior.

      2. Is it possible to increase the word length to 12 bits / 16bits and observe the clock for these lengths.

      3. Another thing to possibly try is change sampling edge (to be different from the current settings) and check.

    Regards

     Vasanth

  • Hello Vasanth,

    1. I set 8 bits per word and 1 word per frame. Then I wrote

    *SPSA_CH2 = SPCR2_CH2_ADDR;
    do 
    {
    	asm (" NOP ");
    }while (!(Tx_Ready_Chk = *SPSD_CH2 & 0x0002));
    *DXR1_CH2 = (short) CmdWrd;

    Repeated above for three times. Everything works fine. There is no extra clock and SPI works exactly.

    2.Yes, I increased words to 12/16 bits then set 3 words per frame. It fails.

    3. I changed sampling edge (tried all 4 possible ways) but still there is no improvement.

    In short, if I configure only one word frame everything works fine (with any number of bits per word) but if I configure multiple words per frame something is going wrong.

    Kindly help.

    Thank You,

    Aravind Chakravarti,

    Accord Software and systems Pvt., LTD.

  • Hello Aravind,

    Below metioned details can be the reason for the clock behavior, that you are observing.

    Refered to Spru302b section 2.7.2

    "It is important to note that even if multiple words are consecutively transferred, the BCLKX signal is always stopped and the BFSX signal returns to the inactive state after a packet transfer. When consecutive packet transfers are performed, this leads to a minimum idle time of two bit-periods between each packet transfer".

    According to this explanation, even though you are trying to send multiple words, it works like one word per frame. Looks like this is the constraint in McBSP supporting SPI mode.

    Regards

     Vasanth

  • Hello Vasanth,

    I do not think so, because the registers XCR2 & RCR2 clearly give provision for 'Multiple Word Transfer' in a single frame. That means, it should be possible to send, multiple words in a single frame.

    As you mentioned, BCLKX signal is stops after every word transfer, that is exactly what we wanted and it is also behaving same (as it can be seen from snap-shot). The only problem what we are having is, after transferring single word  we are not getting exact clocks in the consecutive transfer.

    I guess, some minor problem is there in my configuration. If you (or anyone who is looking this thread) are having any code where multiple words are sent though single frame in McBSP configured for SPI mode?? Can you please share here??

    Thank you,

    Aravind Chakravarti,

    Accord Software & Systems,

    Bangalore.

  • Hello Aravind,

    can you check the delay between the two transfers ? Is the delay mentioned in the Reference set accomodated ? From the snapshot that you shared for me it looks its less than two bit-periods.

    Can you confirm on the above.

    Also, Regarding XCR & RCR these registers are also being used for other McBSP functions and not just in SPI mode.

    Regards

     Vasanth

  • Hello Vasanth,

    Yes, you are correct. XCR & RCR being used for other McBSP functions also.

    As told in the datasheet I had set 1 bit data delay (in XCR2 & RCR2).

    Now also I am seeing same timings as attached in snapshot. I think, its correct right?? (please see the snapshot posted on April 28th). The delay between CHIP_SELECT (i.e., FSX) & CLOCK (i.e.,BCLKX)  is 1 bit period.

    And I am not sure about delay between two words. I dont know how processor decided that delay.

    Thank you for helping me! With so much of patience :)

  • Hello Aravind.

    I did check internally on this and looks like " Clock stop mode works with only single-phase frames ((R/X)PHASE=0) and one word per frame "  with respect to McBSP in SPI mode.

    Regards

     Vasanth