• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 101 subscribers
  • Views 163 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

GPIO interrupt

yaron apel
Intellectual 280 points
Other Parts Discussed in Thread: TMS320C5515

Hi

in "TMS320C5515/14/05/04/VC05/VC04 DSPGeneral-Purpose Input/Output (GPIO) User's Guide"

it is said:

"When an interrupt occurs on an enabled GPIO pin, the GPIO interrupt flag registers (IOINTFLG1 and IOINTFLG2) latch the corresponding bit to a "1". The interrupt signal to the CPU will be kept low until all flag bits in the IOINTFLG1 and IOINTFLG2 registers are cleared"

what happens if during gpio ISR, triggered by one GPIO, another flag (of a different GPIO) is raised (and is not cleared upon exiting the ISR).

will I get another interrupt? Or am I stuck till I clear the second bit raised?

thanks

Yaron

  • 0
    TI__Genius 12575 points

    Hi,

    As mentioned in the GPIO User guide, The Interrupt signal to the CPU will be kept low until all flag bit in the IOINTFLG1/2 are cleared. So if you get another GPIO Interrupt while the previous being served and INTFLGs are not cleared, then you wouldn't get another interrupt (As all GPIO are tied a single interrupt).

    You need to check in the INTFLG for any other Interrupts occured before you clear it (in your GPIO ISR). If you see multiple interrupts then you need to prioritize occordingly. 

    Hope the above information helps.

    Regards

     Vasanth