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configuring i2s on 5535 as Master

Hi All...

How can I get a frame sync of 8KHz or 16KHz exactly from I2S with it being configured as MASTER with 16 bit mono operation..? What should be the values of FSDIV and CLKDIV to achieve this if System Clock is 100MHz..?

Regards,

Ashok

  • You should always calculate back starting from the frame sync and decide the system clock based on FSDIV and CLKDIV. You should not fix the CPU at 100MHz.

    Refer to section 10.2.2 I2S Clock Generator of http://www.ti.com/lit/ug/spruh87d/spruh87d.pdf.

    - Pratap.

  • Thanks Pratap...

    What if my MIPS requirement says that the system clock should be at 100 MHz..?

    Regards,

    Ashok

  • As per the computations as given by the page u referred, I see that for a bit width of 16, mono mode, 8KHz as the sampling frequency, the required System Clock is 32.768 MHz. How do I program the DSP to give this system clock..?

  • Ashok,

    For a given framesync and clock requirements of I2S, there can be multiple system clocks at which you can derive the required FS/CLK. You need to adjust the the CLKDIV based on the minimum CPU requirement of your system.

    Take the case of example described in the document. You can derive the clock value of 1.536 at CPU clocks 3.072, 6.144, 12.288, 24.576, 49.152 and 98.304 MHz by selecting CLKDIV as 0, 1, 2, 3, 4 and 5 respectively.

    - Pratap.

  • Thanks Pratap,

    I understood the example. There his requirement was 1.536 MHz. Here for 16 Bits, the FSDIV is 1 so 2^(FSDIV+3) = 16. So for 8KHz, 8000*16 = 128000 = 128 KHz. So with the maximum available CLKDIV of 256, we can get System clock as 128000*256 = 32768000 = 32.768 MHz. That is the maximum what we can achieve.

    If we want 16KHz, then we can use a system clock of 65.536MHz. These are the maximum what we can achieve for 8K and 16K sampling respectively.

    Please correct me if I'm wrong.

    Regards,

    Ashok

  • Ashok,

     2^(FSDIV+3) need not be exactly 16 in case of 8KHz. It should be at least 16 but can also be more to achieve higher bit clock. By taking FSDIV as 2 you can configure CPU clock to 65MHz even for 8KHz. But it is the maximum CPU clock your system can have either for 8K or 16K.

    In general, flexibility to configure CPU clock as you need will be limited when I2S is working as master. Best option is to have codec as master so that I2S operation will be independent of CPU clock.

     

    - Pratap

     

  • Thanks a lot Pratap. Now I'm using 65MHz as system clock to get the required 8KHz and 16KHz sampling rates. And the code is working fine.

    Thanks & Regards,

    Ashok